inference/research
verifiedmedium · 0.75updated 2026-10-11

Hailo-10H Generative AI Processor

asic-other Hailo Structure-Driven Dataflow Architecture (Gen-2) 2024

Fields

id
accelerators/hailo-10h
Vendor
asic-other
Architecture
Hailo Structure-Driven Dataflow Architecture (Gen-2)
Release year
2024
Form factors
m2
VRAM (GB)
8
Memory type
LPDDR4X (Hailo-10H M.2 module: 4GB or 8GB LPDDR4X)
Bandwidth basis
Hailo-10H features a direct LPDDR4/4X memory interface. Per-chip memory bus width and bandwidth in GB/s are not published on the product specification page.
Peak FLOPS
precisionint4tflops40denseyesvendor_claimyessource_idainv-hailo-10h-product-pagebasisvendor-spec-sheetbasis_detailHailo-10H official product specification: 40 TOPS INT4 performance.precisionint8tflops20denseyesvendor_claimyessource_idainv-hailo-10h-product-pagebasisvendor-spec-sheetbasis_detailHailo-10H official product specification: 20 TOPS INT8 performance (listed as 40|20 TOPS INT4|8).
Unified memory
no
Consumer part
no
notes
Hailo-10H is Hailo second-generation AI accelerator targeting edge generative AI (LLMs and VLMs). It expands on the dataflow architecture of Hailo-8 by adding a direct external LPDDR4/LPDDR4X interface to support multi-gigabyte generative models. Compute performance is 40 TOPS INT4 and 20 TOPS INT8. Typical power consumption is 2.5W (typical), but maximum bare-die TDP is not published. M.2 Key M module includes 4GB or 8GB on-module LPDDR4/4X over PCIe Gen3 x4. 2026-10-11 MERGE: two crawlers read two different Hailo pages. The general product page (ainv-hailo-10h-product-page) gives the LPDDR4/4X interface and TOPS but no capacity; the M.2 module page (hailo-10h-m2-product-page) states 4GB or 8GB LPDDR4X. Capacity taken from the module page, interface detail kept from the product page. Both sources declared. memory_bandwidth_gbps and memory_bus_bit stay null: neither page publishes them.

Notes

Hailo-10H is Hailo second-generation AI accelerator targeting edge generative AI (LLMs and VLMs). It expands on the dataflow architecture of Hailo-8 by adding a direct external LPDDR4/LPDDR4X interface to support multi-gigabyte generative models. Compute performance is 40 TOPS INT4 and 20 TOPS INT8. Typical power consumption is 2.5W (typical), but maximum bare-die TDP is not published. M.2 Key M module includes 4GB or 8GB on-module LPDDR4/4X over PCIe Gen3 x4.

2026-10-11 MERGE: two crawlers read two different Hailo pages. The general product page (ainv-hailo-10h-product-page) gives the LPDDR4/4X interface and TOPS but no capacity; the M.2 module page (hailo-10h-m2-product-page) states 4GB or 8GB LPDDR4X. Capacity taken from the module page, interface detail kept from the product page. Both sources declared. memory_bandwidth_gbps and memory_bus_bit stay null: neither page publishes them.

Cross-references

Interconnect (1)