PCI Express 3.0

x16, PER DIRECTION. THE CONVENTION, STATED EXPLICITLY AS THIS REPO'S REPEATED FAILURE MODE: PCIe figures are quoted PER LANE PER DIRECTION, and a PCIe lane is dual-simplex (independent TX and RX conductor pairs), so a per-lane-per-direction figure at a given lane count is ALREADY the complete figure for that direction and must NOT be halved a second time. PCI-SIG's own ladder entry (w7p-pcisig-pcie5-faq-verified), verbatim: 'PCIe 3.0 added support for 8.0 Gigabits/second/Lane/direction of raw bandwidth' - 'per direction' is PCI-SIG's own wording. Storing 15.75 (or 31.5) as an aggregate is a 2x ERROR that halves the interconnect; storing the bidirectional 31.5 as per-direction is the same error inverted. Arithmetic: 8 GT/s x 128/130 (128b/130b) / 8 = 0.985 GB/s per lane per direction, x16 = 15.754 GB/s PER DIRECTION; bidirectional aggregate is 31.5 GB/s. RAW unencoded: 8 x 16 / 8 = 16.0 GB/s per direction. ENCODING: NRZ with 128b/130b line coding - this is the generation that INTRODUCED 128b/130b, replacing 8b/10b, which is why the Gen2->Gen3 payload ratio is 1.97x rather than 2x (98.46% vs 80% encoding efficiency). PCI-SIG publishes the rate but not the line code, so the coding is cited to w7p-wikipedia-pcie-link-performance, table row '3.0 | 2010 | 128b/130b | 8.0 GT/s | 0.985 | 1.969 | 3.938 | 7.877 | 15.754' and prose, verbatim: 'PCIe 1.x uses an 8b/10b encoding scheme, resulting in a 20% (= 2/10) overhead on the raw channel bandwidth'. The table's column footnote states the convention outright: 'In each direction (each lane is a dual simplex channel).' Same convention as pcie-gen4 (31.5 per direction), pcie-gen5 (63.0), pcie-gen6 (121.0) and pcie-gen7 (242.0).

Point-to-point host-to-device (root complex to endpoint), up to 16 lanes. Becomes a shared fabric only via PCIe switches or host bridges.

Optional PCIe switch, store-and-forward, no in-network reduction.

PCIe 3.0 is the generation used by the Horizon Journey 5 automotive SoC (PCIe Gen3 2-lane). At 15.75 GB/s per direction at x16, it is roughly 28x below NVLink 4's 450 GB/s per direction per GPU. THE DIRECTION CONVENTION IS THE SAME AS EVERY OTHER pcie-gen* RECORD: per lane per direction, not aggregate - see bandwidth_basis. ENCODING CHANGE WORTH KNOWING, because it breaks the clean doubling: PCIe 3.0 is where 128b/130b replaced 8b/10b, so the payload ratio from Gen2 (8.0 per direction) to Gen3 (15.75) is 1.97x even though the GT/s rate went 5.0 -> 8.0, and the ratio from Gen3 to Gen4 (31.5) is then exactly 2x. So 128b/130b makes the FIRST step off the 8b/10b era sub-linear and the rest of the NRZ era linear - the mirror image of what PAM4 does at Gen6 (see pcie-gen6 and pcie-gen7, where the sub-linear step is Gen5 -> Gen6 at 1.92x because flit framing at 242B/256B is less efficient than 128b/130b). Any table of this family that shows a uniform 2x per generation across gens 1-7 is either quoting raw rates or has silently mixed encoding conventions; the payload per direction ladder is 4.0 / 8.0 / 15.75 / 31.5 / 63.0 / 121.0 / 242.0 and the two non-2x steps are Gen2->Gen3 (1.97x) and Gen5->Gen6 (1.92x).