Hailo-8 AI Processor
asic-other Hailo Structure-Driven Dataflow Architecture 2020
Fields
id
accelerators/hailo-8Vendor
asic-other
Architecture
Hailo Structure-Driven Dataflow Architecture
Release year
2020
Form factors
m2pcie
Memory type
sram (fully integrated on-chip memory architecture, no external DRAM required)
Bandwidth basis
Hailo-8 architecture integrates all memory on-chip with zero external DRAM interface. On-chip SRAM bandwidth and capacity are not published in numerical terms by the vendor.
Peak FLOPS
precisionint8tflops26denseyesvendor_claimyessource_idainv-hailo-8-product-pagebasisvendor-spec-sheetbasis_detailHailo-8 official product page: up to 26 tera-operations per second (TOPS) INT8.
Unified memory
no
Consumer part
no
notes
Hailo-8 is an edge AI inference processor designed for vision and neural network workloads. Features a proprietary structure-driven dataflow architecture that eliminates external DRAM, integrating all neural compute memory on-die. Delivers 26 TOPS INT8. Typical power consumption is reported as ~2.5W, but no official bare-chip maximum TDP is published in the spec table, so tdp_w is left null. Form factors include M.2 2242/2280 modules, mPCIe, and Century PCIe card. Host interface supports PCIe Gen3 x4.
Notes
Hailo-8 is an edge AI inference processor designed for vision and neural network workloads. Features a proprietary structure-driven dataflow architecture that eliminates external DRAM, integrating all neural compute memory on-die. Delivers 26 TOPS INT8. Typical power consumption is reported as ~2.5W, but no official bare-chip maximum TDP is published in the spec table, so tdp_w is left null. Form factors include M.2 2242/2280 modules, mPCIe, and Century PCIe card. Host interface supports PCIe Gen3 x4.