inference/research
draftlow · 0.50updated 2026-10-05

Iluvatar CoreX BI-V100 (Tiangai 100) training card

asic-other Iluvatar general GPU (2nd gen) 2021
This record is a draft. Not yet verified. Provisional. Treat every number on this page as provisional.

Fields

id
accelerators/iluvatar-bi-v100-mr-v100
Vendor
asic-other
Architecture
Iluvatar general GPU (2nd gen)
Release year
2021
Process (nm)
7
Form factors
pcie
VRAM (GB)
32
Memory type
hbm2
Bandwidth basis
None available. Iluvatar publishes memory TYPE and CAPACITY on both cards - HBM2 32 GB on the BI-V100 training card, HBM2E 32 GB on the MR-V100 inference card - and the 16 GB HBM2E for the smaller MR-V50, but publishes NO bandwidth figure, no bus width and no compute throughput on either page. That is remarkable for a vendor product page: the memory capacity and the TDP are both stated, and the two numbers a roofline needs are both absent. Sources cn-iluvatar-tianggai100 and cn-iluvatar-zhikai100.
TDP (W)
250
Unified memory
no
Consumer part
no
notes
SPLIT 2026-10-05: this record used to be 'BI-V100 (Tiangai 100) / MR-V100 (Zhikai 100)' and carried memory_type 'hbm2e', which is correct for the MR-V100 and WRONG for the BI-V100. The two are now separate records - this one for the BI-V100, and iluvatar-mr-v100-zhikai100 for the MR-V100 - because they differ in memory technology, power, slot width, role and release date, and because a single record can hold only one memory_type. THE VENDOR'S OWN WORDING, verbatim from the BI-V100 产品规格 table: '内存 | 32 GB DRAM HBM2'. That is 'DRAM' and 'HBM2' in one field, and it is the only place in this slice where a vendor prints the word 'DRAM' beside an HBM part. It is recorded as printed rather than normalised to 'hbm2': the sibling MR-V100 page prints plain '32 GB HBM2E' with no 'DRAM', so the difference between the two strings is the vendor's own, and silently 'correcting' it would erase the only evidence that Iluvatar distinguishes its training line from its inference line. The stored value 'hbm2' is the closest single enum-style token and the 'DRAM' qualifier is preserved in this note and in the source record rather than being discarded. NO COMPUTE FIGURE, confirmed on this pass: the page's 产品特点 section claims '业界领先的高算力和高能效比' and '在百余个算法模型的测试平均性能可媲美主流产品' - industry-leading compute, average performance across 100+ models comparable to mainstream products - with no number attached. flops stays EMPTY and that is the verified correct state. SPARSITY: no footnote, no '2:4', no sparsity wording anywhere on the page. Moot given nothing numeric is printed, and recorded so a future reader does not assume a figure exists to be halved. THE AMBIGUOUS INTERCONNECT STRING IS CONFIRMED VERBATIM and still unresolved in the vendor's own words: the 接口 row prints '共享 64 GB/s 主控双向带宽' and '共享 64 GB/s 片间互联带宽' - the same 64 GB/s figure for host bidirectional bandwidth and for device-to-device interconnect, with '共享' (shared) doing ambiguous work. Whether these are one shared resource or two parallel ones is not stated, and flagging it beats resolving it. At 64 GB/s of device-to-device, scale-up is extremely weak and BI-V100 multi-card work is effectively PCIe- and RoCE-bound - which is the single most unusual interconnect number in this slice. Other facts unchanged: 7 nm (the vendor's 'first wholly domestic 7nm GPGPU' claim), 250 W board power, full-height full-length DUAL-slot passive card, PCIe Gen4 x16. VENDOR: Iluvatar CoreX (天数智芯), founded end-2015 by Li Yunpeng (ten years at Oracle), unicorn valuation over USD 1bn in 2024, HKEX IPO 8 January 2026 (ticker 9903), strong government ties including the Shanghai Supercomputer Center; corporate turbulence worth recording - Diao Shijing was appointed chairman and CEO in May 2021 and taken away for investigation in an anti-graft probe in July 2022. Software is DeepSpark, an open community. MEMORY_BUS_WIDTH: STILL NULL. The vendor publishes neither a bus width nor a pin rate for this part, so the 64 GB/s interconnect figures above cannot be used to derive one, and NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong.

Notes

SPLIT 2026-10-05: this record used to be 'BI-V100 (Tiangai 100) / MR-V100 (Zhikai 100)' and carried memory_type 'hbm2e', which is correct for the MR-V100 and WRONG for the BI-V100. The two are now separate records - this one for the BI-V100, and iluvatar-mr-v100-zhikai100 for the MR-V100 - because they differ in memory technology, power, slot width, role and release date, and because a single record can hold only one memory_type. THE VENDOR'S OWN WORDING, verbatim from the BI-V100 产品规格 table: '内存 | 32 GB DRAM HBM2'. That is 'DRAM' and 'HBM2' in one field, and it is the only place in this slice where a vendor prints the word 'DRAM' beside an HBM part. It is recorded as printed rather than normalised to 'hbm2': the sibling MR-V100 page prints plain '32 GB HBM2E' with no 'DRAM', so the difference between the two strings is the vendor's own, and silently 'correcting' it would erase the only evidence that Iluvatar distinguishes its training line from its inference line. The stored value 'hbm2' is the closest single enum-style token and the 'DRAM' qualifier is preserved in this note and in the source record rather than being discarded. NO COMPUTE FIGURE, confirmed on this pass: the page's 产品特点 section claims '业界领先的高算力和高能效比' and '在百余个算法模型的测试平均性能可媲美主流产品' - industry-leading compute, average performance across 100+ models comparable to mainstream products - with no number attached. flops stays EMPTY and that is the verified correct state. SPARSITY: no footnote, no '2:4', no sparsity wording anywhere on the page. Moot given nothing numeric is printed, and recorded so a future reader does not assume a figure exists to be halved. THE AMBIGUOUS INTERCONNECT STRING IS CONFIRMED VERBATIM and still unresolved in the vendor's own words: the 接口 row prints '共享 64 GB/s 主控双向带宽' and '共享 64 GB/s 片间互联带宽' - the same 64 GB/s figure for host bidirectional bandwidth and for device-to-device interconnect, with '共享' (shared) doing ambiguous work. Whether these are one shared resource or two parallel ones is not stated, and flagging it beats resolving it. At 64 GB/s of device-to-device, scale-up is extremely weak and BI-V100 multi-card work is effectively PCIe- and RoCE-bound - which is the single most unusual interconnect number in this slice. Other facts unchanged: 7 nm (the vendor's 'first wholly domestic 7nm GPGPU' claim), 250 W board power, full-height full-length DUAL-slot passive card, PCIe Gen4 x16. VENDOR: Iluvatar CoreX (天数智芯), founded end-2015 by Li Yunpeng (ten years at Oracle), unicorn valuation over USD 1bn in 2024, HKEX IPO 8 January 2026 (ticker 9903), strong government ties including the Shanghai Supercomputer Center; corporate turbulence worth recording - Diao Shijing was appointed chairman and CEO in May 2021 and taken away for investigation in an anti-graft probe in July 2022. Software is DeepSpark, an open community. MEMORY_BUS_WIDTH: STILL NULL. The vendor publishes neither a bus width nor a pin rate for this part, so the 64 GB/s interconnect figures above cannot be used to derive one, and NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong.

Cross-references

Interconnect (1)