inference/research
verifiedhigh · 0.85updated 2026-10-11

Kinara Ara240

asic-other Programmable RISC-V Dataflow Discrete NPU 2024

Fields

id
accelerators/kinara-ara240
Vendor
asic-other
Architecture
Programmable RISC-V Dataflow Discrete NPU
Release year
2024
Form factors
m2
VRAM (GB)
16
Peak FLOPS
precisionint8tflops40denseyesvendor_claimyessource_idnxp-kinara-ara240-dnpubasisvendor-spec-sheetbasis_detailNXP DNPU product catalog states Ara240 'Delivers up to 40 eTOPS* of AI performance, efficiently handling Generative AI and transformer-based models at the edge. *eTOPS means equivalent TOPS.' Recorded as 40 TOPS INT8.unit—
Unified memory
no
Consumer part
no
notes
REAL VENDOR: Kinara, Inc. (acquired by NXP Semiconductors). Set to 'asic-other' because the schema enum does not include 'kinara' or 'nxp'. Ara240 (formerly Ara-2) is Kinara's second-generation discrete neural processing unit (DNPU) built on a programmable RISC-V dataflow architecture. NXP specifies up to 40 equivalent TOPS (eTOPS) for GenAI, LLMs, and vision transformer workloads. Shipped as standalone chips and an Ara240 16GB M.2 module (and USB module). Software stack includes the Ara SDK with model optimization tools, integrating with ONNX and TensorFlow/LiteRT model pipelines. MEMORY AND POWER FIGURES: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-11). NXP publishes the 16GB module capacity on the Ara240 16GB M.2 Module, but omits the exact DRAM memory type (LPDDR4 vs LPDDR5), bus width, and memory bandwidth in GB/s. TDP wattage is also not specified on the primary product catalog page. Per repo rules, missing fields remain honest nulls rather than extrapolated values.

Notes

REAL VENDOR: Kinara, Inc. (acquired by NXP Semiconductors). Set to 'asic-other' because the schema enum does not include 'kinara' or 'nxp'. Ara240 (formerly Ara-2) is Kinara's second-generation discrete neural processing unit (DNPU) built on a programmable RISC-V dataflow architecture. NXP specifies up to 40 equivalent TOPS (eTOPS) for GenAI, LLMs, and vision transformer workloads. Shipped as standalone chips and an Ara240 16GB M.2 module (and USB module). Software stack includes the Ara SDK with model optimization tools, integrating with ONNX and TensorFlow/LiteRT model pipelines. MEMORY AND POWER FIGURES: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-11). NXP publishes the 16GB module capacity on the Ara240 16GB M.2 Module, but omits the exact DRAM memory type (LPDDR4 vs LPDDR5), bus width, and memory bandwidth in GB/s. TDP wattage is also not specified on the primary product catalog page. Per repo rules, missing fields remain honest nulls rather than extrapolated values.

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