NVIDIA GeForce RTX 5070
nvidia blackwell (GB203) 2025
Fields
id
accelerators/local-nvidia-rtx-5070Vendor
nvidia
Architecture
blackwell (GB203)
Release year
2025
Process (nm)
4
Form factors
pcie
VRAM (GB)
12
Memory type
gddr7
Memory bus (bit)
192
Memory bandwidth (GB/s)
672
Bandwidth basis
GDDR7 28 Gbps data rate x 192-bit / 8 = 672 GB/s. Both numbers are printed directly by the RTX Blackwell architecture whitepaper, Table 6 (GeForce RTX 5070 vs 4070 vs 3070): 'Memory Clock (Data Rate) 28 Gbps', 'Memory Bandwidth 672 GB/sec', 'Memory Interface 192-bit'. AUDIT CORRECTION 2026-10-04: the basis previously read 'GDDR7 24 Gbps data rate x 192-bit / 8 = 672 GB/s', which is arithmetically false - 24 Gbps x 192-bit / 8 = 576 GB/s, not 672. The stored 672 GB/s was always right; only the stated derivation was wrong. 28 Gbps is confirmed independently by NVIDIA's GeForce RTX 5070 Family product page spec table.
Peak FLOPS
precisionfp32tflops30.9denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 29.4; the stored figure did not match any row of the cited table.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp32 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp16tflops61.7denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 58.7; the stored figure did not match any row of the cited table.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp16 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionbf16tflops61.7denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 58.7; the stored figure did not match any row of the cited table.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own bf16 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp8tflops123.5denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 117.4; the stored figure did not match any row of the cited table.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp8 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp8tflops246.9densenovendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 234.8; the stored figure did not match any row of the cited table.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp8 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule. Full reasoning for this row retained verbatim in notes.precisionfp4tflops493.9denseyesvendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 234.8; the stored figure did not match any row of the cited table.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp4 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:true as printed. Full reasoning for this row retained verbatim in notes.precisionfp4tflops987.8densenovendor_claimyessource_idconsumer-nvidia-rtx-blackwell-gpu-architecture-whitepapernotesAUDIT CORRECTION 2026-10-04. Whitepaper Table 6 row (RTX 5070 column) prints this as a 'dense/sparse' pair under footnote 2, 'Effective TOPS / TFLOPS using the Sparsity Feature': Peak FP32 TFLOPS (non-Tensor) 30.9; Peak FP16/BF16 Tensor TFLOPS with FP32 Accumulate 61.7/123.5; Peak FP8 Tensor TFLOPS with FP32 Accumulate 123.5/246.9; Peak FP4 Tensor TFLOPS with FP32 Accumulate (FP4 AI TOPS) 493.9/987.8. Previously stored 469.6; the stored figure did not match any row of the cited table. Independent corroboration from NVIDIA's own GeForce RTX 5070 Family product page, which advertises '988 AI TOPS' - that is the sparse FP4 figure 987.8, and the old stored 469.6 matched neither.basisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp4 for NVIDIA GeForce RTX 5070 (source of record: 'NVIDIA RTX Blackwell GPU Architecture whitepaper (GeForce RTX 50 series)', kind: whitepaper). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule. Full reasoning for this row retained verbatim in notes.
TDP (W)
250
Unified memory
no
Consumer part
yes
notes
Entry-level Blackwell consumer part. 12 GB GDDR7 on a 192-bit bus at 28 Gbps, 672 GB/s. 250 W TGP. AUDIT 2026-10-04: ALL SEVEN flops rows in this record were wrong, and the memory bandwidth basis was wrong, and the error pattern is diagnostic. Every stored figure had been derived by doubling the record's own (also wrong) fp32 value of 29.4 rather than read off the whitepaper table: fp16 = 2 x 29.4 = 58.7, fp8 = 4 x 29.4 = 117.4, fp4 = 8 x 29.4 = 234.8. The whitepaper's actual figures are fp32 30.9, fp16 61.7, fp8 123.5, fp4 493.9 - i.e. FP4 is 4x FP8, not 2x, so the record had FP4 understated by 2.1x on top of the shared ~5% base error. The fp32 value 29.4 matches no published clock for this part: the whitepaper Table 6 gives 'GPU Boost Clock (MHz) 2512' (= 6144 cores x 2 x 2512 MHz = 30.87 TFLOPS -> 30.9) and NVIDIA's product page gives boost 2.51 GHz / base 2.33 GHz. OLD VALUES, all corrected: fp32 29.4 -> 30.9; fp16 58.7 -> 61.7; bf16 58.7 -> 61.7; fp8 dense 117.4 -> 123.5; fp8 sparse 234.8 -> 246.9; fp4 dense 234.8 -> 493.9; fp4 sparse 469.6 -> 987.8; memory_bandwidth_basis '24 Gbps' -> '28 Gbps'. Internal cross-check that the correction is right: the sibling record nvidia-rtx-5070-ti stores fp32 43.9 and 896 GB/s, both of which reproduce exactly from its own whitepaper row (8960 x 2 x 2452 MHz; 28 Gbps x 256-bit / 8), so this record was the odd one out within its own family. Dense/sparse FLAGS were correct on every row and did not need changing - the failure here was arithmetic, not the inverted-flag class. The 12GB VRAM remains the critical constraint for local LLM inference: a 70B model at 4-bit quantization needs ~35GB, which exceeds this card's capacity. Suitable for models up to ~13B at 4-bit or ~7B at 8-bit. Lowest-VRAM part in the 50-series and the first to be genuinely capacity- rather than compute-constrained for LLM workloads.
INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen5'], from the vendor's own spec table (source the GeForce RTX 5070 family product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.
Notes
Entry-level Blackwell consumer part. 12 GB GDDR7 on a 192-bit bus at 28 Gbps, 672 GB/s. 250 W TGP. AUDIT 2026-10-04: ALL SEVEN flops rows in this record were wrong, and the memory bandwidth basis was wrong, and the error pattern is diagnostic. Every stored figure had been derived by doubling the record's own (also wrong) fp32 value of 29.4 rather than read off the whitepaper table: fp16 = 2 x 29.4 = 58.7, fp8 = 4 x 29.4 = 117.4, fp4 = 8 x 29.4 = 234.8. The whitepaper's actual figures are fp32 30.9, fp16 61.7, fp8 123.5, fp4 493.9 - i.e. FP4 is 4x FP8, not 2x, so the record had FP4 understated by 2.1x on top of the shared ~5% base error. The fp32 value 29.4 matches no published clock for this part: the whitepaper Table 6 gives 'GPU Boost Clock (MHz) 2512' (= 6144 cores x 2 x 2512 MHz = 30.87 TFLOPS -> 30.9) and NVIDIA's product page gives boost 2.51 GHz / base 2.33 GHz. OLD VALUES, all corrected: fp32 29.4 -> 30.9; fp16 58.7 -> 61.7; bf16 58.7 -> 61.7; fp8 dense 117.4 -> 123.5; fp8 sparse 234.8 -> 246.9; fp4 dense 234.8 -> 493.9; fp4 sparse 469.6 -> 987.8; memory_bandwidth_basis '24 Gbps' -> '28 Gbps'. Internal cross-check that the correction is right: the sibling record nvidia-rtx-5070-ti stores fp32 43.9 and 896 GB/s, both of which reproduce exactly from its own whitepaper row (8960 x 2 x 2452 MHz; 28 Gbps x 256-bit / 8), so this record was the odd one out within its own family. Dense/sparse FLAGS were correct on every row and did not need changing - the failure here was arithmetic, not the inverted-flag class. The 12GB VRAM remains the critical constraint for local LLM inference: a 70B model at 4-bit quantization needs ~35GB, which exceeds this card's capacity. Suitable for models up to ~13B at 4-bit or ~7B at 8-bit. Lowest-VRAM part in the 50-series and the first to be genuinely capacity- rather than compute-constrained for LLM workloads. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen5'], from the vendor's own spec table (source the GeForce RTX 5070 family product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.