inference/research
draftlow · 0.55updated 2026-10-08

MetaX C550 (flagship OAM GPGPU, training and inference)

asic-other MetaX XCORE (proprietary GPGPU core IP) 2024
This record is a draft. Not yet verified. Provisional. Treat every number on this page as provisional.

Fields

id
accelerators/metax-c550
Vendor
asic-other
Architecture
MetaX XCORE (proprietary GPGPU core IP)
Release year
2024
Form factors
oam
VRAM (GB)
64
Memory type
hbm2e
Bandwidth basis
None available. MetaX's product page for the C550 states 'large-capacity high-bandwidth memory' and '64GB GPU Memory' but publishes no bandwidth figure. The 896 GB/s figure on the product page refers to the MetaXLink interconnect bandwidth, not memory bandwidth.
TDP (W)
450
Unified memory
no
Consumer part
no
notes
THE HIERARCHY POINT: the C550 is MetaX's flagship OAM module GPGPU, compliant with OAM 1.5/2.0 standards, and the successor to the C500. It is the most well-documented MetaX part. VENDOR-PUBLISHED SPECIFICATIONS (MetaX product page, primary source): 64 GB GPU memory with end-to-end ECC protection, MetaXLink interconnect enabling 8-card full-interconnect topology at up to 896 GB/s, OAM 1.5/2.0 compliant form factor, maximum board power 450 W, virtualization with software-defined partitioning at 1% granularity. The C550 3D Mesh Supernode supports up to 8 servers and 64 cards with 3D Mesh topology. NO COMPUTE THROUGHPUT FIGURE IS PUBLISHED — MetaX does not state TFLOPS or TOPS for the C550 on its product page. The MXMACA software stack is compatible with mainstream GPU ecosystems. MetaX IPO'd on the SSE on 17 December 2025 (ticker 688802). The C550 is significant because it is the first MetaX part with a clearly documented interconnect specification (896 GB/s MetaXLink). Vendor is 'asic-other' because 'metax' is not in the schema enum. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). MetaX's C550 product page publishes HBM2E capacity and bandwidth but no memory-bus width and no per-pin data rate. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch. NEGATIVE QUALIFIED 2026-10-05: the claim that MetaX publishes no compute figure is PROBABLY TRUE but is NOT established by a completed read of the vendor's pages, and the difference matters. MetaX's own product pages (cid=107&id=21 for the C500, id=35 for the C550) fail with 'All scraping engines failed to retrieve content from this URL. Engines tried: [playwright, fetch]', and cn-metax-c550's existing note already records a plain probe returning HTTP 403. A Wayback capture DOES exist and renders (timestamp 20260609083954) and confirms the vendor has pages for all four parts of this record - N100, N260, N300, C500, C550, C500X, C588, C600 - none of which is reachable from here. So for MetaX the honest statement is 'the vendor pages exist and are unreadable by three client types', not 'the vendor publishes nothing'. WHAT IS ESTABLISHED: a secondary compilation carries a much fuller C500 table - FP32 54 TFLOPS '(vector 18 + matrix 36)', TF32 140, FP16 280, BF16 280, INT8 560 TOPS, 64GB HBM2e, 7 MetaXLink ports to 64 cards - which is 3.5x the Wikipedia-sourced figures on the SAME part. That disagreement is recorded and NOT propagated: the compilation explicitly labels process, TDP and bandwidth as undisclosed or estimated, so it is not a citable source for the rows it does not mark as estimates, and importing its compute figures while its memory figures are estimates would smuggle an estimate into a field that does not need one. A future pass with access to the vendor page has a 3.5x question to settle here, not a gap to fill. See w5a-metax-no-compute-figure-confirmed-two-methods.

Notes

THE HIERARCHY POINT: the C550 is MetaX's flagship OAM module GPGPU, compliant with OAM 1.5/2.0 standards, and the successor to the C500. It is the most well-documented MetaX part. VENDOR-PUBLISHED SPECIFICATIONS (MetaX product page, primary source): 64 GB GPU memory with end-to-end ECC protection, MetaXLink interconnect enabling 8-card full-interconnect topology at up to 896 GB/s, OAM 1.5/2.0 compliant form factor, maximum board power 450 W, virtualization with software-defined partitioning at 1% granularity. The C550 3D Mesh Supernode supports up to 8 servers and 64 cards with 3D Mesh topology. NO COMPUTE THROUGHPUT FIGURE IS PUBLISHED — MetaX does not state TFLOPS or TOPS for the C550 on its product page. The MXMACA software stack is compatible with mainstream GPU ecosystems. MetaX IPO'd on the SSE on 17 December 2025 (ticker 688802). The C550 is significant because it is the first MetaX part with a clearly documented interconnect specification (896 GB/s MetaXLink). Vendor is 'asic-other' because 'metax' is not in the schema enum. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch.

MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). MetaX's C550 product page publishes HBM2E capacity and bandwidth but no memory-bus width and no per-pin data rate. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.

NEGATIVE QUALIFIED 2026-10-05: the claim that MetaX publishes no compute figure is PROBABLY TRUE but is NOT established by a completed read of the vendor's pages, and the difference matters. MetaX's own product pages (cid=107&id=21 for the C500, id=35 for the C550) fail with 'All scraping engines failed to retrieve content from this URL. Engines tried: [playwright, fetch]', and cn-metax-c550's existing note already records a plain probe returning HTTP 403. A Wayback capture DOES exist and renders (timestamp 20260609083954) and confirms the vendor has pages for all four parts of this record - N100, N260, N300, C500, C550, C500X, C588, C600 - none of which is reachable from here. So for MetaX the honest statement is 'the vendor pages exist and are unreadable by three client types', not 'the vendor publishes nothing'. WHAT IS ESTABLISHED: a secondary compilation carries a much fuller C500 table - FP32 54 TFLOPS '(vector 18 + matrix 36)', TF32 140, FP16 280, BF16 280, INT8 560 TOPS, 64GB HBM2e, 7 MetaXLink ports to 64 cards - which is 3.5x the Wikipedia-sourced figures on the SAME part. That disagreement is recorded and NOT propagated: the compilation explicitly labels process, TDP and bandwidth as undisclosed or estimated, so it is not a citable source for the rows it does not mark as estimates, and importing its compute figures while its memory figures are estimates would smuggle an estimate into a field that does not need one. A future pass with access to the vendor page has a 3.5x question to settle here, not a gap to fill. See w5a-metax-no-compute-figure-confirmed-two-methods.

Cross-references

Interconnect (2)