NVIDIA GB300 (Blackwell Ultra GPU as fitted in the GB300 NVL72 rack, per-GPU figures)

8 TB/s is the GB300 NVL72 column of the Blackwell Ultra datasheet's per-GPU row 'GPU Memory | Bandwidth 279 GB HBM3E | 8 TB/s' (source w3a-nvidia-gb300-blackwell-ultra-datasheet-4169750). memory_bus_bit is NULL AND THAT IS THE HONEST STATE: NVIDIA publishes no bus width in bits and no per-pin data rate for the Blackwell Ultra HBM3E interface, and neither does the GB300 product page. It is NOT back-computed from the aggregate. (For what it is worth, nvidia-b300 in this repo records memory_bus_bit 8192 as the inferred Blackwell-generation HBM3e width; that value is inherited from the B200/GB200 generation and is not vendor-published for Blackwell Ultra either. It is deliberately NOT copied here, because copying an inference across a generation boundary is exactly the mistake this repo's dens/sparse notes exist to prevent. The corroborating check that 8192 IS the right shape: system figure 576 TB/s / 72 GPUs = 8 TB/s per GPU, matching the per-GPU row, so the aggregate is self-consistent - but self-consistency does not establish the width.)

CREATED 2026-10-04 to resolve two dangling references: flops/sd-hardware-sensitivity and flops/sd-production-deployments both carry 'nvidia-gb300' in affected_by_hardware, and the audit found no such accelerator record existed - GB300 appeared in this repo ONLY as benchmark records and as a supply record for the rack. WHAT THIS RECORD IS, AND WHY IT IS NOT SIMPLY A COPY OF nvidia-b300: this record is the GB300 NVL72 COLUMN of the Blackwell Ultra datasheet - that is, the per-GPU configuration as actually fitted in the 72-GPU rack, which is 279 GB HBM3E at 8 TB/s and up to 1,400 W. data/accelerators/nvidia-b300.json is the Blackwell Ultra part as it ships in the 8-GPU HGX B300 baseboard, whose datasheet column prints 270 GB at 7.7 TB/s and up to 1,100 W. Those are DIFFERENT products with DIFFERENT memory capacity, DIFFERENT bandwidth and DIFFERENT power ceilings, on the same silicon generation. The distinction was previously invisible in this repo because nvidia-b300 had absorbed both columns; this record restores the GB300-column figures under the GB300 name so the two stop being conflated. Every flops row above is re-derived from the datasheet's own footnote rather than copied from nvidia-b300, and the two records agree on all of them (the FP4 dense 15,000 and the FP8 dense 5,000 are the same on both, because both read the same per-GPU row under the same footnotes) - the disagreement between the records is in vram_gb, memory_bandwidth_gbps, tdp_w and memory_bus_bit only. STATUS IS contested, NOT verified, and the reason is the FP4 sparse/dense contradiction with NVIDIA's own product page, set out on the fp4 row above. Two NVIDIA-published documents give dense FP4 for the same silicon as 15 (datasheet, labelled Sparse|Dense pair) and 10 (product page, 'all Tensor Core ... with sparsity'). The tensor rows are otherwise consistent across both documents. This is exactly the AGENTS.md case: two sources, same quantity, different values, reason knowable - keep both, set contested. TWO THINGS THIS RECORD DELIBERATELY DOES NOT CLAIM. (1) The naming. NVIDIA's own materials are not self-consistent about what 'GB300' names: the product page and datasheet use it for the 72-GPU RACK; the two MLPerf v6.1 submission records in this repo (bench-mlperf-v6-1-nvidia-gb300-8gpu-llama2-70b-offline / -server, and the two CoreWeave records) describe hardware as 'NVIDIA GB300-288GB', a THIRD capacity figure matching neither 279 nor 270. This record is filed at per-GPU granularity to match how nvidia-gb200-nvl72 is filed, and the id 'nvidia-gb300' is inherited from the references that needed resolving. The 288 GB discrepancy is NOT reconciled here and is recorded as an open upstream naming question. (2) Rack power. NVIDIA publishes the per-GPU TDP ceiling (1,400 W) and the system memory-bandwidth figure (576 TB/s), but NOT the GB300 rack's total power. Do not infer one from the per-GPU ceiling; the same restraint is already recorded on the supply record for the rack. INTERCONNECT: nvlink-5 and nvswitch-5 for the 130 TB/s 72-GPU NVLink domain ('Total NVLink Switch Bandwidth 130 TB/s'; per-GPU row 'Interconnect Fifth-Generation NVLink: 1.8 TB/s'), plus pcie-gen6 from the same row ('PCIe Gen6: 256 GB/s'). Note the per-GPU NVLink figure of 1.8 TB/s here is a HARDWARE-DESIGN maximum quoted on the spec sheet and is roughly 2x what any measured v6.1 submission on this platform sustains per GPU - see the two GB300 benchmark records in this repo, where NVIDIA's own 8-GPU slice delivers 16,433 tok/s per GPU against CoreWeave's full 72-GPU rack at 15,779 tok/s per GPU. That 9x-the-GPUs-for-8.6x-the-throughput result is the single most useful fact in this repo about scale-up fabric at small model sizes. THE 37 TB 'FAST MEMORY' FIGURE IS NOT A MEMORY-CAPACITY NUMBER and must not be read as one: it is a rack total that NVIDIA defines as a fast-access pool (20 TB of it is HBM3E per the system row 'GPU Memory 20 TB | Bandwidth Up to 576 TB/s'), and 20 TB / 72 = 278 GB per GPU, close to but not identical with the 279 GB per-GPU HBM3E figure. The 514 GB/GPU implied by dividing 37 TB by 72 appears in nvidia-b300's notes as a third quantity again. Three numbers, three different definitions, none of them a bus width.