NVIDIA H200 NVL

CORRECTED 2026-10-03: no value changed; the dense flags on this record were re-verified against NVIDIA's own H200 spec table (https://www.nvidia.com/en-us/data-center/h200), which footnotes exactly the rows at issue - the table's closing footnote reads '1 Preliminary specifications. May be subject to change. 2 With sparsity.' and footnote marker 2 sits on TF32 Tensor Core, BFLOAT16, FP16, FP8 and INT8 but NOT on FP64, FP64 Tensor Core or FP32. So in the H200 NVL column 835 / 1,671 / 1,671 / 3,341 / 3,341 are all SPARSE and dense is exactly half: 417.5 / 835.5 / 835.5 / 1,670.5 / 1,670.5 - which is what this record already stored, with every dense flag already true. Worth stating explicitly because the sparse numbers (1,671 BF16, 3,341 FP8) are the ones that circulate in comparison tables and blogs, and they are 2x this card's real dense throughput. A quick self-check a reader can run on any NVIDIA part: the printed number should equal exactly 2x the dense figure for every tensor row, and the FP32 row should NOT be halved. AUDIT CORRECTION: the dense/sparse flag on the tensor rows was inverted. FP16 835.5 / FP8 1670.5 TFLOPS are DENSE; NVIDIA prints 1,671/3,341 'With sparsity'. These rows were previously flagged dense:false, which wrongly told a reader they were sparse. The stored numbers are correct dense values. CRITICAL: NVIDIA prints 835 TF32 / 1,671 BF16+FP16 / 3,341 FP8+INT8 for H200 NVL, all WITH SPARITY - dense is half. H200 NVL is the air-cooled enterprise card: same 141GB HBM3e / 4.8TB/s as the SXM part, so it is a drop-in capacity upgrade for H100 NVL, at reduced Tensor throughput (835 vs 989 sparse) and a lower 600W cap. NVIDIA's spec table carries a 'preliminary specifications' footnote. MIG profiles differ from SXM: 7 MIGs @16.5GB (NVL) vs 7 @18GB (SXM). Bus width inferred. The 'other' row is FP64 30 TFLOPS (dense) - this schema's precision enum has no fp64 member.