NVIDIA NVLink 4.0

PER LINK, UNIDIRECTIONAL. DERIVED, NOT PUBLISHED - NVIDIA prints no per-link rate for this generation. NVIDIA's spec table gives 900 GB/s NVLink bandwidth per GPU for the fourth generation, and that figure is BIDIRECTIONAL AGGREGATE across 18 links; NVIDIA's own word for it is 'total': 'Fourth-generation NVIDIA NVLink provides a 3x bandwidth increase on all-reduce operations and a 50% general bandwidth increase over the prior generation NVLink with 900 GB/sec TOTAL bandwidth for multi-GPU IO' (w7n-nvidia-hopper-architecture-in-depth-blog), and the H100 product page likewise says 900 GB/s of GPU-to-GPU interconnect. Per-direction aggregate is therefore 450 GB/s per GPU, and per link per direction is 900 / 18 / 2 = 25 GB/s, which is the recorded value. THE ARITHMETIC IDENTITY THAT MAKES THE DERIVATION TRUSTWORTHY: 18 x 25 x 2 = 900 exactly, and the same identity holds on every generation in this family, so a derivation that fails it is wrong. This is the single most commonly mangled number in the domain, and it fails in BOTH directions at once: 'NVLink 4 is 50 GB/s' is the bidirectional per-link rate (2x too high for a per-direction read), '900 GB/s' is the bidirectional per-GPU total (2x too high again per-direction, and 18x too high if read as per-link).

Point-to-point GPU-to-GPU links, exposed on both sides of the card (NVLink bridge on PCIe SKUs such as H100 NVL, direct in SXM/ HGX baseboards). Switched via NVSwitch 4 for a non-blocking 8-GPU server domain.

NVSwitch 4 (see nvswitch-4) turns the 8-GPU node from a partial mesh into a non-blocking all-to-all fabric at the same 900 GB/s per-GPU rate.

Hopper generation. HEADLINE CAPABILITY, the third required quantity for this generation, and it is a two-part claim that must not be collapsed into one number: NVIDIA states 'Fourth-generation NVIDIA NVLink provides a 3X BANDWIDTH INCREASE ON ALL-REDUCE OPERATIONS and a 50% GENERAL BANDWIDTH INCREASE over the prior generation NVLink' (w7n-nvidia-hopper-architecture-in-depth-blog). Those are different quantities - a 3x on all-reduce specifically, a 1.5x on general bandwidth - and the gap between them is the generation's real story: 600 GB/s to 900 GB/s per-GPU bidirectional aggregate is only 1.5x, while the all-reduce figure is 3x, so most of NVLink 4's benefit to collective-heavy work came from the switch-side and addressing improvements rather than from the raw link rate, which did not move at all (still 25 GB/s per direction per link, as on Gen2 and Gen3). A reader who stores only 'NVLink 4 is 1.5x faster' understates what a TP all-reduce actually gains; a reader who stores only '3x' overstates what a non-collective transfer gains. Note the 3x claim is an all-reduce throughput claim and should be read as a vendor claim on a collective, not as a link property. Inference consequence: tensor-parallel sharding wants the highest per-direction fabric rate available, because every layer boundary ships activations across the link. The bidirectional aggregate figure that dominates marketing is not what a single collective move sees. NVLink 4 holds the per-link rate flat at 25 GB/s per direction and raises the link count 12 -> 18, so the gain is links, not link speed - a useful reminder that aggregate fabric bandwidth is link_count x per-link rate x 2. Inference practical note: H100 NVL pairs expose only the NVLink bridge path, so a 2-GPU H100 NVL node has the same 450 GB/s per-direction aggregate as a fully-wired SXM H100 despite being PCIe-hosted. PROVENANCE 2026-10-05: the per-link figure is DERIVED (NVIDIA publishes no per-link rate for this generation), unlike nvlink-1, nvlink-2 and nvlink-3 whose per-link figures are transcribed verbatim from NVIDIA whitepapers - see gotcha w7n-nvlink-per-link-rate-is-derived-not-published-except-gen1. The direction and per-link-vs-per-GPU axes are filed as gotcha w7n-nvlink-per-gpu-aggregate-vs-per-link-rate.