inference/research
verifiedhigh · 0.90updated 2026-10-03

NVIDIA GeForce RTX 4080 (16 GB)

nvidia ada (AD103) 2022

Fields

id
accelerators/nvidia-rtx-4080
Vendor
nvidia
Architecture
ada (AD103)
Release year
2022
Process (nm)
4
Form factors
pcie
VRAM (GB)
16
Memory type
gddr6x
Memory bus (bit)
256
Memory bandwidth (GB/s)
716.8
Bandwidth basis
GDDR6X 22.4 Gbps data rate x 256-bit / 8 = 716.8 GB/s (NVIDIA Ada whitepaper Appendix B, AD103 'GeForce RTX 4080 16 GB' column)
Peak FLOPS
precisionfp32tflops48.7denseyesvendor_claimyessource_idconsumer-nvidia-ada-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp32 for NVIDIA GeForce RTX 4080 (16 GB) (source of record: 'NVIDIA Ada GPU Architecture whitepaper v2.02', kind: whitepaper). Recorded dense:true as printed.precisionfp16tflops97.5denseyesvendor_claimyessource_idconsumer-nvidia-ada-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own fp16 for NVIDIA GeForce RTX 4080 (16 GB) (source of record: 'NVIDIA Ada GPU Architecture whitepaper v2.02', kind: whitepaper). Recorded dense:true as printed.precisionbf16tflops97.5denseyesvendor_claimyessource_idconsumer-nvidia-ada-gpu-architecture-whitepaperbasisvendor-whitepaperbasis_detailTranscribed from the vendor's own bf16 for NVIDIA GeForce RTX 4080 (16 GB) (source of record: 'NVIDIA Ada GPU Architecture whitepaper v2.02', kind: whitepaper). Recorded dense:true as printed.
TDP (W)
320
Unified memory
no
Consumer part
yes
notes
Mid-rung Ada consumer part, 9728 CUDA cores, 2505 MHz boost, 320 W TGP, 65536 KB L2. Included mainly as the bandwidth counterpoint for the 16 GB VRAM tier. Inference-relevant: 16 GB at 716.8 GB/s is ~71% of the 4090's 1008 GB/s. But the binding constraint at 16 GB is capacity, not bandwidth - a 16 GB pool leaves almost no headroom for KV cache once a 13B-class model is quantised, while a 24 GB card fits the same model with room. Read the two axes together. FP16 97.5 TFLOPS is with FP32 accumulate, dense; the sparse figure is 195. Ada whitepaper prints both as '97.5/195'. ACCUMULATE-MODE DISAMBIGUATION (why there is only one fp16/fp8 entry each): NVIDIA's whitepapers print separate tensor rows per accumulate mode, and the same numeric value can appear as DENSE in one row and SPARSE in another. E.g. on the 4090 'Peak FP16 Tensor TFLOPS with FP16 Accumulate 330.3/660.6' and 'Peak FP16 Tensor TFLOPS with FP32 Accumulate 165.2/330.4' - so 330.3 is DENSE-with-FP16-accumulate and SPARSE-with-FP32-accumulate. Encoding that as a single dense:false entry would be wrong. The flops array here therefore records ONE entry per precision, always the FP32-accumulate figure, because that is what LLM inference kernels use; the FP16-accumulate variants are stated in this note instead of being mislabeled as sparse. 4080 FP16-accumulate figure: fp16 dense 194.9 / sparse 389.8 TFLOPS. The recorded fp16 97.5 entry is FP32-accumulate dense. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen4'], from the vendor's own spec table (source the GeForce RTX 4080 family product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.

Notes

Mid-rung Ada consumer part, 9728 CUDA cores, 2505 MHz boost, 320 W TGP, 65536 KB L2. Included mainly as the bandwidth counterpoint for the 16 GB VRAM tier.

Inference-relevant: 16 GB at 716.8 GB/s is ~71% of the 4090's 1008 GB/s. But the binding constraint at 16 GB is capacity, not bandwidth - a 16 GB pool leaves almost no headroom for KV cache once a 13B-class model is quantised, while a 24 GB card fits the same model with room. Read the two axes together.

FP16 97.5 TFLOPS is with FP32 accumulate, dense; the sparse figure is 195. Ada whitepaper prints both as '97.5/195'.

ACCUMULATE-MODE DISAMBIGUATION (why there is only one fp16/fp8 entry each): NVIDIA's whitepapers print separate tensor rows per accumulate mode, and the same numeric value can appear as DENSE in one row and SPARSE in another. E.g. on the 4090 'Peak FP16 Tensor TFLOPS with FP16 Accumulate 330.3/660.6' and 'Peak FP16 Tensor TFLOPS with FP32 Accumulate 165.2/330.4' - so 330.3 is DENSE-with-FP16-accumulate and SPARSE-with-FP32-accumulate. Encoding that as a single dense:false entry would be wrong. The flops array here therefore records ONE entry per precision, always the FP32-accumulate figure, because that is what LLM inference kernels use; the FP16-accumulate variants are stated in this note instead of being mislabeled as sparse. 4080 FP16-accumulate figure: fp16 dense 194.9 / sparse 389.8 TFLOPS. The recorded fp16 97.5 entry is FP32-accumulate dense. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen4'], from the vendor's own spec table (source the GeForce RTX 4080 family product page's 'Technology Support' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.

Cross-references

Interconnect (1)