NVIDIA RTX 6000 Ada Generation

Datasheet spec table prints 'Memory interface 384-bit' and 'Memory bandwidth 960 GB/s' directly (implying a 20 Gbps GDDR6 part at 384-bit). Note the Ada whitepaper's AD102 column prints 1008 GB/s, which is the 21 Gbps GDDR6X consumer part on the same 384-bit width - do not carry one number onto the other card.

AUDIT 2026-10-03 (NVIDIA dense/sparse convention re-verified from the primary whitepaper PDF, no values changed): NVIDIA's GeForce RTX Blackwell architecture whitepaper (source consumer-nvidia-rtx-blackwell-gpu-architecture-whitepaper, images.nvidia.com/aem-dam/Solutions/geforce/blackwell/) prints every tensor row in the form 'DENSE/SPARSE' and defines the second number in a single footnote that is identical on every appendix page: 'Effective TOPS / TFLOPS using the Sparsity Feature'. Every 'Peak ... Tensor TFLOPS' and 'Peak INT8 Tensor TOPS' row on the sheet therefore carries that marker, while the 'non-Tensor' rows (FP32/FP16/BF16 non-tensor, Peak INT32 TOPS non-Tensor) and the RT TFLOPS row do NOT. Each sparse row was re-checked against that sheet page by page and every dense:false row on this record corresponds to a printed second number, with its dense twin present as a separate dense:true row. Note the sheet's own footnote 1, 'Peak rates are based on GPU Boost Clock' - these are boost-clock peaks, not sustained, and not measured. The RTX 6000 Ada Generation product brief prints a single 'Peak FP8 Tensor TFLOPS with FP16 Accumulate 1457' style row set with the sparsity footnote marking the second value; fp8 1457 stored here as dense:false is the sparse figure and its dense twin is stored separately. This card is the workstation Ada die at full enablement, so its numbers sit above the RTX 4090's despite the same AD102 family - which is the recurring trap in Ada: workstation and consumer parts from one silicon generation are not interchangeable on tensor throughput, only on architecture.Workstation part: 18176 CUDA cores, 568 4th-gen Tensor cores, 142 3rd-gen RT cores, 300 W total board power, PCIe 4.0 x16, dual slot full height, 4x DisplayPort 1.4a. 48 GB GDDR6 WITH ECC - a capacity and reliability tier no consumer Ada card offers, which is why this card stayed common for local LLMs after the 4090 arrived. PRECISION CAVEAT: the datasheet's headline 'Tensor performance 1457.0 TFLOPS' carries footnote 4 'Effective FP8 teraFLOPS (TFLOPS) using the new sparsity feature'. So 1457 is FP8 WITH 2:4 sparsity; the dense FP8 figure is 728.5. Both are recorded above with dense flags. Any comparison of this card's '1457 TFLOPS' against a Blackwell card's '4000 AI TOPS' compares sparse-FP8 against sparse-FP4 - different operations, not a like-for-like speedup. No NVLink ('NVIDIA NVLink: No' in the datasheet), so multi-GPU is PCIe-bound. ECC is the meaningful differentiator for long-running inference servers, where a silent bit flip in a 24 GB consumer card is unrecoverable. INTERCONNECT FILLED 2026-10-04: interconnect was empty; it now reads ['pcie-gen4'], from the vendor's own spec table (source NVIDIA doc 2504660's spec-table 'System interface' row). SCALE-UP IS ABSENT AND THAT IS THE POINT: this part has no NVLink and no other GPU-to-GPU fabric, so the host link is the ONLY interconnect a multi-GPU deployment has. Do not infer a fabric from the presence of a PCIe value, and do not read the Gen number as a multi-GPU capability.