SambaNova SN40L Reconfigurable Dataflow Unit (RDU)

NULL, AND HERE IS WHAT WAS LOOKED FOR (2026-10-11). arXiv:2405.07518 reports 520 MiB on-chip PMU SRAM providing hundreds of TB/s on-chip memory bandwidth, 64 GiB co-packaged HBM (per-socket GB/s not stated as a discrete number), and DDR DRAM tier with peak bandwidth over 200 GB/s, with DDR-to-HBM model loading over 1 TB/s across an 8-socket SN40L node. Per-chip HBM bandwidth in GB/s is not published directly by the vendor in the whitepaper.

SambaNova SN40L is fabricated on TSMC 5nm using 2.5D Chip-on-Wafer-on-Substrate (CoWoS) packaging containing two SN40L Reconfigurable Dataflow Dies (RDDs) and co-packaged HBM. It features a unique three-tier memory hierarchy: 520 MiB on-chip PMU SRAM, 64 GiB on-package HBM, and up to 1.5 TiB of directly attached DDR DRAM (via pluggable DIMMs). Peak compute is 638 BF16 TFLOPS per socket across 1040 PCUs. TDP is not published at the individual socket level (16-socket rack is air-cooled in standard 19-inch form factor delivering 10.2 BF16 PFLOPS aggregate roofline). All numbers transcribed directly from SambaNova technical paper (arXiv:2405.07518) and blog post. 2026-10-11 MERGE: a second crawler (PR #59) created a record for the same chip from the vendor RDU datasheet (asic-sambanova-sn40l, 640 TFLOPS BF16, 64 GB HBM2E, 520 MB SRAM). This record keeps the arXiv:2405.07518 whitepaper figure of 638 TFLOPS because that is the number actually quoted in the source, not rounded. The 638-vs-640 gap is a rounding difference between the paper and the datasheet, not a conflict; both documents are declared as sources so the difference is visible. No number changed.