SambaNova SN40L: Scaling the AI Memory Wall with Dataflow and Composition of Experts (arXiv:2405.07518)

Fields

id

sources/ainv-sambanova-sn40l-paper

URL

https://arxiv.org/abs/2405.07518

Publisher

SambaNova Systems

Kind

whitepaper

Published

2024-05-11

Accessed

2026-10-11

notes

First-party technical paper by SambaNova Systems architecture team (Prabhakar et al.) detailing the SN40L Reconfigurable Dataflow Unit (RDU), TSMC 5nm process, 2.5D CoWoS package, dual Reconfigurable Dataflow Dies (RDD), 638 BF16 TFLOPS, 520 MiB on-chip PMU SRAM, 64 GiB co-packaged HBM, and up to 1.5 TiB DDR DRAM.

Notes

First-party technical paper by SambaNova Systems architecture team (Prabhakar et al.) detailing the SN40L Reconfigurable Dataflow Unit (RDU), TSMC 5nm process, 2.5D CoWoS package, dual Reconfigurable Dataflow Dies (RDD), 638 BF16 TFLOPS, 520 MiB on-chip PMU SRAM, 64 GiB co-packaged HBM, and up to 1.5 TiB DDR DRAM.

Cross-references

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