Google TPU v5e: 197 BF16 TFLOPS per chip

Vendor-published per-chip specification. Single TensorCore with 4 MXUs (128x128 each). 16 GB HBM at 819 GB/s. 256-chip pod on 2D torus with ICI 400 GB/s bidirectional per chip.

Vendor-published peak compute specification. The 197 TFLOPS is the theoretical BF16 peak per chip. No inference throughput (tokens/sec) is published by Google for TPU v5e. The INT8 figure is 393 TOPS (2x BF16). v5e is the cost-optimized part with the lowest compute-to-byte ratio (240 FLOP/byte BF16). LOAD-CONDITION AUDIT (bq- 2026-10-04). SCENARIO: NOT STATED by the source - absent, not inferred. A throughput figure with no scenario cannot be placed against an MLPerf Offline or Server number (they are different measurements; on identical hardware the Offline-minus-Server difference is negative in 5 of 9 systems measured). ABSENT CONDITIONS (5 of 7 checked: model, hardware, batch-or-concurrency, input length, output length, engine version, warmup): - engine version: unrecoverable from asic-tpu-v5e-specs - engine_id=alt-tpu-perf-guide is named but no build/commit/container digest is published - batch/concurrency: unrecoverable from asic-tpu-v5e-specs - would need the achieved in-flight batch or the --max-concurrency value - input length: unrecoverable from asic-tpu-v5e-specs - would need the run's ISL or the prepared dataset's input-length profile - output length: unrecoverable from asic-tpu-v5e-specs - would need the run's OSL or the harness's configured max_tokens - warmup: unrecoverable from asic-tpu-v5e-specs - would need the raw harness log's warmup phase or the benchmark command line (loadgen min_duration/min_query_count, or trtllm-bench --warm_up N / --num_runs N) None of these were filled in. A plausible value is worse than an absent one: it would be trusted.