Google Cloud TPU v5e

Per-chip figures. The docs give only a BF16 per-chip peak of 197 TFLOPS; no FP8, INT8, FP32 or TF32 per-chip number is published, so those fields are left out rather than inferred. INT8 is published only at pod scale (100 PetaOps for the 256-chip pod), which is consistent with 197 BF16 x2. HBM2 at 16 GB is the smallest capacity in the TPU line and gives a low compute-to-byte ratio (240 FLOP/byte BF16), so v5e is firmly memory-bound for batch-1 decode; Google positions it as a cost-optimized part where TCO matters more than peak. Pod is 256 chips on a 2D torus, ICI 1600 Gbps per chip. One TensorCore per chip with 4 MXUs. Notably, v5e serving is single-host only up to 8 chips; multi-host serving needs Saxml. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.