Qwen3.6-35B-A3B NVFP4 W4A16 MoE on the Marlin backend: GSM8K accuracy (reference W4A16 path)

The reference number for this checkpoint: 0.9136 GSM8K with the Marlin W4A16 path versus 0.9037 on the FlashInfer b12x W4A4 path - a 0.99 pp / 13-answer gap attributable purely to backend dispatch on identical weights. Because MoE expert GEMMs dominate the FLOP mix here, a per-expert precision mistake is proportionally more damaging than the same mistake on a dense linear layer. Compare nvfp4-w4a16-flashinfer-b12x-moe-gsm8k. See gotcha flashinfer-b12x-moe-runs-w4a16-as-w4a4. INTERCONNECT IDS FILLED 2026-10-04: interconnect_ids was empty; it now carries the interconnect list of the accelerator record(s) this run names (nvidia-rtx-pro-6000-blackwell). BASIS AND ITS LIMITS, stated because this field is easy to over-read: it records the FABRIC PRESENT IN THE HARDWARE CONFIGURATION, which is how every previously-filled record in this repo reads it, not traffic measured over that fabric. The clearest evidence for that convention is that single-GPU records already carry a scale-up fabric here - trtllm-llama31-8b-fp8-h100-1k1k-tps is 1x H100 at TP=1 and carries ['nvlink-4','nvswitch-4'] - and that host-link-only records carry a PCIe value (arc-pro-b70-mlperf-v6-1-llama2-70b-offline-tokens carries ['pcie-gen5'] on 4x Arc Pro B70, which has no GPU-to-GPU fabric at all). So a value here does NOT mean the interconnect was exercised by this particular workload, and must not be cited as evidence that it was. Whether the run actually crossed that fabric is a question about TP/EP/PP size, which this repo records in methodology, not here. NOT INVENTED: nothing was filled where the accelerator record itself carries no interconnect, so this field stays empty for any part whose own record has none - which is the honest state for a single-socket Apple sOC and for parts whose vendor publishes no host interface.