CDNA4 Matrix Core MFMA instruction precision support (MXFP8, MXFP6, MXFP4)

CDNA4 (gfx950) Matrix Cores add native hardware support for OCP MX (micro-scaling) formats: MXFP8, MXFP6, and MXFP4. Execution resources for 16-bit and smaller data types are 2x the prior generation. The key addition is MXFP6/MXFP4 at 9.2 PFLOPS (MI350X) / 10.1 PFLOPS (MI355X) - 2x the OCP-FP8 rate. This means 4-bit inference is natively accelerated on CDNA4, not emulated. MXFP8 uses block-scaled representation (per-block scaling factors) which provides better accuracy than per-tensor FP8 for the same bit width. CDNA4 does NOT have a native TF32 matrix path - AMD's footnote says 'TF32 support through software emulation'. The vector FP16 path (157.3 TFLOPS on MI355X) is 16x slower than the matrix FP16 path (2500 TFLOPS), a new asymmetry on CDNA4. DANGLING REF, LEFT UNRESOLVED (2026-10-04 cross-reference repair): affected_by_hardware also carries 'gfx950', an AMD GPU ARCHITECTURE CODE, not a record id, and it spans more than one accelerator record: amd-instinct-mi350x, amd-instinct-mi355x and amd-instinct-mi350p are all CDNA4 (gfx950). Because one value in this field resolves to several accelerator records, it cannot be rewritten to a single id, and the field is typed as accelerator ids so this is a mixed-bucket value that belongs in a sibling field for architecture codenames. Left unchanged deliberately.