AMD Instinct MI350X

'8 TB/s' per the AMD spec table, which lists 'Memory Clock 8 GHz' on an 8192-bit interface. AMD does not publish the arithmetic; treat as 'up to 8 TB/s' vendor figure. AUDIT CORRECTION: 8192-bit x 8 Gb/s per pin / 8 = 8,192 GB/s, not 8,000. The correct per-pin rate is 7.81 Gbps (8000 x 8 / 8192). (The generic 'HBM3E = 5.0 Gbps' assumption that a mechanical audit would apply gives 5,120 GB/s and is wrong for this part: MI350-series HBM3E runs at ~7.81 Gbps per pin, and AMD's own spec table lists 'Memory Clock 8 GHz'.)

AUDIT 2026-10-03 (AMD's dense/sparse convention established from the MI350X page itself and applied to every row; no values changed): this page is the cleanest statement of AMD's convention anywhere in the lineup, because it prints BOTH forms side by side with explicit labels - 'Peak Half Precision Matrix (FP16) Performance 2.3 PFLOPs' (DENSE) and 'Peak Half Precision Matrix (FP16) Performance with Structured Sparsity 4.6 PFLOPs' (SPARSE) - and likewise for OCP-FP8 (4.6 / 9.2), INT8 (4.6 / 9.2) and BF16 (2.3 / 4.6). So AMD's convention is: the unlabelled-by-sparsity row is DENSE and is exactly half the 'with Structured Sparsity' row. Every dense flag on this record is correct against that rule. THE SUBTLE PART, and the one a mechanical audit gets wrong: the MXFP4 and MXFP6 rows on the same page print '9.2 PFLOPs' with NO sparsity variant at all, so 9.2 is DENSE for those formats - not sparse, and not half of anything on this sheet. A reader who assumes 'AMD's biggest printed number is always the sparse one' would wrongly halve the MXFP4 row to 4.6. The two 9.2 TFLOPS-per-PFLOP figures on this part mean different things by precision. Also relevant to any AMD-vs-NVIDIA comparison built from this part's spec page: AMD's own comparison chart here prints 'FP16/BF16 Tensor / FP16/BF16 Matrix (Sparsity) 4.5 | 4.6' and 'FP8 Tensor / OCP-FP8 Matrix (Sparsity) 9 | 9.2' for B200 SXM5 - i.e. AMD quotes NVIDIA's SPARSE numbers (4.5 and 9 PFLOPS). NVIDIA's own Blackwell datasheet footnotes exactly those as sparse, dense being 2.5 and 5. Using AMD's chart as if it were dense understates B200 by 2x. Air-cooled sibling of the MI355X. Same CDNA4 silicon, same 288 GB HBM3E, same 8 TB/s, same 8192-bit interface, same 185B transistors, same 8 XCDs / 256 CUs / 16,384 SPs / 1024 matrix cores. It differs ONLY in clock and power: 2200 MHz and 1000W (passive OAM) versus the MI355X's 2400 MHz and 1400W (passive & active). AMD's own MI355X brochure explains the split: MI355X's higher power budget lets it 'sustain higher performance over time, minimizing throttling and maximizing throughput during prolonged or intensive workloads'. So the real difference is sustained, not burst. Same eight-die caveat: 288 GB is one package address space across 8 XCDs, not multiple devices. Compute ratio to MI355X is 2300/2500 = 0.92 on FP16 matrix, matching the 2200/2400 = 0.917 clock ratio exactly - consistent with the same die. Two fp16 entries on purpose: 144.2 TFLOPS is the VECTOR path, 2300 TFLOPS is the MATRIX path. TF32 is software-emulated on CDNA4 (AMD footnote), so there is no native TF32 figure to carry over from MI300X. Sparse figures are exactly 2x dense. MXFP6/MXFP4 at 9200 PFLOPs are the headline inference datatypes and are quoted without a sparse companion. 7 scale-up Infinity Fabric links at 153 GB/s (product page; the MI355X datasheet gives the more precise 153.6) plus one 128 GB/s scale-out link. ROCm LLVM target gfx950. FP64 (AUDIT 2026-10-04, row added): 72.1 TFLOPs, vector and matrix both, dense. Recorded on the sibling nvidia-b200 comparison as AMD's 2x-B200 HPC pitch: AMD's chart plots MI350X FP64 72.1 vs B200 SXM 5's 37.