AMD Infinity Fabric (CDNA / MI100 class: 3 links, 92 GB/s bidirectional per link, 23 GT/sec, 16 lanes)

PER LINK, PER DIRECTION, 16-WIDE - and this is the figure AMD does NOT print, so it is derived. AMD'S OWN DERIVATION FORMULA, from the CDNA 2 white paper endnote MI200-29: 'Peak theoretical inter GDC to GDC data transport rate performance is calculated by Baud Rate * # lanes * # directions * # links / 8 = GB/s per card.' The '# directions' multiplier is AMD confirming that every figure in this endnote family is BIDIRECTIONAL, and it is the reason this record stores the PER-DIRECTION value in bandwidth_gbps while AMD's board tables print the bidirectional one. AMD's own documents give the three inputs separately: the ROCm MI100 microarchitecture page states the fabric links run at '23 GT/sec'; the MI100 product page board table states 'Infinity Fabric(TM) Links: 3' and 'Peak Infinity Fabric(TM) Link Bandwidth: 92 GB/s'; the CDNA 2 white paper endnote MI200-43 states 'three links providing up to 276 GB/s peak theoretical GPU P2P transport rate bandwidth performance per GPU card'. THE THREE AGREE EXACTLY, which is what makes this record solid rather than inferred: (a) 23 GT/s x 16 lanes / 8 = 46 GB/s per direction; (b) 23 x 16 x 2 / 8 = 92 GB/s bidirectional, which is the board table's 92 verbatim; (c) 276 / 3 = 92 GB/s per link bidirectional, matching (b), and 3 x 92 = 276 is the per-card GPU-to-GPU total. SO: 46 GB/s per direction is the per-link figure; 92 GB/s is the same link counted both ways; 276 GB/s is the 3-link GPU-to-GPU aggregate. THREE FIGURES, THREE SEPARATE MEANINGS, all first-party.

GPU-to-GPU: a hive of up to four MI100 PCIe cards, fully connected and COHERENT (AMD uses the word 'coherent' here, unlike the later PCIe-attached nodes), reached over three AMD Infinity Fabric ports per card running at 23 GT/sec. Inter-GPU links require the GPUs to sit in neighbouring PCIe slots with an AMD Infinity Fabric bridge card installed. HOST PATH IS SEPARATE AND SLOWER: 'each processor can host up to four AMD Instinct(TM) GPUs that are attached using PCIe Gen 4 links at 16 GT/sec, which corresponds to a peak bidirectional link bandwidth of 32 GB/sec'. So on MI100 the host attach is 32 GB/s bidirectional while the GPU-to-GPU per-link figure is 92 GB/s bidirectional - the CPU attach path is the SMALLER of the two by nearly 3x, which is the opposite of the intuition that PCIe is the fast general-purpose path, and it is the direct consequence of the fabric being the coherent multi-GPU domain.

No switch part. The four-GPU hive is built from direct point-to-point links, so there is nothing to grow past without adding a bridge card or changing topology.

WHY A NEW RECORD: the repo previously had no Infinity Fabric record for the CDNA / MI100 generation at all - amd-infinity-fabric-link starts at CDNA 3. THE TRAP THIS GENERATION IS WORTH RECORDING: the MI100 board table row 'Peak Infinity Fabric Link Bandwidth 92 GB/s' sits in the same table as 'Bus Type: PCIe 4.0 x16 , PCIe 3.0 x16', so it reads like a host/PCIe figure at a glance. It is not - it is the per-GPU-to-GPU fabric link, bidirectional, and it is larger than the host path on the very same board. AMD DOES NOT PUBLISH for this generation: an 'Nth Gen AMD Infinity Architecture' label. The MI100 page's Supported Technologies row says only 'AMD Infinity Architecture' with no generation number, so unlike MI350X/MI355X (which say '4th Gen AMD Infinity Architecture') this generation cannot be given AMD's own generation label and is keyed to the CDNA generation instead. AMD also does not publish a scale-up/scale-out row split on this page; that split appears only from the MI350 series onward. INFERENCE RELEVANCE: 276 GB/s of GPU-to-GPU against 1.2288 TB/s of HBM2 means the fabric is roughly 4.4x below local memory, so a four-GPU MI100 hive can sustain a model sharded across the hive with a real but bounded arithmetic-intensity penalty - and the 32 GB/s host path is ample for streaming weights in but not for anything the fabric does not cover.