ROCm 'AMD Instinct MI100 microarchitecture' reference - 23 GT/sec fabric links and the host PCIe attach
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sources/w7a-amd-mi100-microarch-if-23gt-and-host-pcieNotes
Gives the CDNA-generation lane rate AND the host attach path for the MI100, which the MI100 product page's 92 GB/s does not decompose. Verbatim: 'each processor can host up to four AMD Instinct(TM) GPUs that are attached using PCIe Gen 4 links at 16 GT/sec, which corresponds to a peak bidirectional link bandwidth of 32 GB/sec' (HOST PATH - 32 GB/s bidirectional, NOT 64, because the MI100 page lists 'PCIe 4.0 x16 , PCIe 3.0 x16' and this sentence describes the 16 GT/sec Gen4 rate); 'Each hive of four GPUs can participate in a fully connected, coherent AMD Instinct(TM) fabric that connects the four GPUs using 23 GT/sec AMD Infinity fabric links' (GPU-TO-GPU - 23 GT/sec, three ports per the product page); and 'the three AMD Infinity Fabric ports that provide high-speed links (23 GT/sec ...) to the other GPUs of the local hive'. Note the sentence 'which corresponds to a peak bidirectional link bandwidth of 32 GB/sec' is AMD explicitly using the word BIDIRECTIONAL for the host figure, which makes the host path direction-safe to quote. Also note this page uses the word COHERENT for the MI100 hive fabric, unlike the PCIe-attached MI300/MI350 nodes.
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