Cambricon MLU-Link (chiplet / multi-chip scale-up)

The scale-up link for the Cambricon MLU370 family, and the record that makes an inverted ratio explicit. PUBLISHED FIGURE: 200 GB/s per chip of MLU-Link chip-to-chip bandwidth, from the vendor's die-level chip overview, alongside a die-level 256 TOPS INT8. The card-level S4/S8 parts publish 192 TOPS INT8 card - exactly half the die figure, because the die figure is for the dual-chiplet X4/X8 configuration - so a reader must not compare the 200 GB/s against the card-level 307.2 GB/s of LPDDR5 bandwidth as though both described the same SKU. THE INVERTED RATIO IS THE POINT, and it is why this record is worth having: on a normal GPU the scale-up fabric is several times FASTER than local memory bandwidth (NVLink 4 at 450 GB/s per direction against 3.35 TB/s of HBM is slower, but Infinity Fabric and NVSwitch exist precisely to keep the ratio from collapsing as memory bandwidth outruns fabric). On MLU370 it is the reverse in character rather than in raw number: 200 GB/s of scale-up against a part with NO HBM at all and only 307.2 GB/s of local LPDDR5 bandwidth means the scale-up link is a large fraction of local bandwidth, which is respectable for a chiplet interconnect on a high-density card and is not the limiting factor for this part. The limiting factor is that MLU370 has no HBM tier, so its arithmetic intensity ceiling is far left of every HBM part in this repo and the card is a high-density inference part rather than a large-model serving part. INFERENCE RELEVANCE: if you do shard an MLU370 across two chips you are not fabric-limited, you are limited by LPDDR5 bandwidth - which is an unusual situation in this repo and worth knowing before optimising the interconnect side. VARIANT CAVEAT: MLU-Link appears on the X4/X8 dual-die train+infer parts; the S4/S8 inference cards do not use it for scale-up. KIND: filed as 'other' because MLU-Link is a proprietary vendor interconnect with no entry in the schema's enum and no analogue in the named families.