Cambricon MLU370 (Siyuan 370) chip overview
spec-sheet
Fields
id
sources/asic-cambricon-mlu370-chipPublisher
Cambricon Technologies
Kind
spec-sheet
Published
2026-10-03
Accessed
2026-10-03
notes
Die-level: chiplet design, 39e9 transistors, 256 TOPS INT8 at die level, MLU-Link 200 GB/s per chip, first cloud AI chip with LPDDR5.
Notes
Die-level: chiplet design, 39e9 transistors, 256 TOPS INT8 at die level, MLU-Link 200 GB/s per chip, first cloud AI chip with LPDDR5.
Cross-references
This record references no other records.