Iluvatar CoreX BI-V100 (Tiangai 100) inter-chip interconnect - 64 GB/s bidirectional, published by the vendor on the card's own interface row as 片间互联

PER LINK, BIDIRECTIONAL AGGREGATE - THE VENDOR'S OWN WORD, NOT AN INFERENCE. The BI-V100 product page's 接口 (interfaces) row reads verbatim: 'PCIe Gen4.0 x 16 lane' / '共享 64 GB/s 主控双向带宽' / '共享 64 GB/s 片间互联带宽'. 双向 means 'bidirectional' and it qualifies BOTH of the 64 GB/s figures, so the recorded 64.0 is the bidirectional aggregate exactly as published, and the per-direction value is 32 GB/s. 共享 means 'shared', indicating the bandwidth is a shared resource rather than a private point-to-point link - the only structural hint the vendor gives, and the reason link_count is recorded as 1 rather than left null: the vendor describes one shared bandwidth, not a port array. NO PER-LINK BREAKDOWN EXISTS TO DIVIDE: there is no port count, no lane width and no signalling standard anywhere on the page, so this figure has NOT been split into per-lane rates and no per-port value has been inferred.

INTER-CHIP, AIMED AT SCALE-UP, WITH NO TOPOLOGY PUBLISHED. The vendor names it 片间互联 (inter-chip interconnect) and lists it on the same interface row as a separate 'PCIe Gen4.0 x 16 lane' host link, so this 64 GB/s figure is NOT the host interface. THE HOST LINK'S OWN PUBLISHED FIGURE IS THE OTHER 64 GB/s (主控 = host controller). THIS IS THE CENTRAL TRAP IN THE RECORD: the card publishes THE SAME 64 GB/s NUMBER TWICE, for two different fabrics, and a reader searching for 'the bandwidth' finds one value that describes both and therefore neither. That is precisely why two records now exist instead of one record with two figures. WHAT IS NOT PUBLISHED ANYWHERE: the number of links, whether the far side is a switch or a peer, whether another vendor's accelerator can attach, the maximum chip count, and any collective or communication-library documentation. Iluvatar publishes no cluster topology, no switch part and no communication library for the BI-V100.

NOT PUBLISHED. No switch, retimer or topology is named in any Iluvatar source this repo holds. scale_out is null rather than false because the vendor is silent on whether the same path is used beyond a host - asserting false would claim the vendor ruled it out, and asserting true would claim they allow it.

ADDED 2026-10-05. This is a GENUINE FABRIC THAT WAS ALREADY IN THE SOURCES AND HAD NO RECORD. The repo was not unaware of the 64 GB/s figure - data/accelerators/iluvatar-bi-v100-mr-v100 states in its memory_bandwidth_basis that 'the vendor prints the same 64 GB/s figure for host and device links and it is therefore an interconnect number, not memory bandwidth'. So the information existed and had been correctly DECLINED as a memory bandwidth, but one of the two figures was never given a home as the interconnect it is. The correct destination for 片间互联 was an interconnect record and it did not exist, so the accelerator listed only 'pcie-gen4' and a reader had no way to learn that Iluvatar publishes a scale-up figure at all. WHY 64 GB/s BIDIRECTIONAL IS A REAL RESULT DESPITE BEING UNIMPRESSIVE: on its own it is a modest number - 32 GB/s per direction against, say, Ascend 950DT's 392 GB/s per direction, a factor of 12. The point of recording it is not that it is fast, it is that it is PUBLISHED, which is rare in this corpus, and that its existence lets the BI-V150 negative below be stated precisely: the previous generation has a figure and the current one has nothing. A reader comparing Iluvatar generations needs both halves of that. THE DIRECTION WORD MATTERS MORE THAN USUAL HERE. Because Iluvatar prints 双向 on the row, this figure is unambiguous where most of this corpus is not, and it puts Iluvatar on the aggregate side of the per-direction-vs-aggregate split alongside Cambricon's '聚合带宽200GB/s Bi-direction' for MLU-Link and Intel's 'Networking (bidirectional)' for Gaudi 3. It is now possible to say that every non-NVIDIA, non-AMD scale-up fabric in this repo whose vendor bothers to state a convention states an AGGREGATE one - see the gotcha w7f-non-nv-am-vendor-conventions. CONFIDENCE 0.75, NOT HIGHER, FOR AN HONEST REASON: the figure itself is quoted verbatim from the vendor and is not in doubt at all. What is missing is everything around it - no topology, no link count, no peer description, no scale figure. The number is certain and the interconnect is largely undocumented, and the gap between those two facts is why the confidence is not at the top of the scale. DO NOT MERGE WITH iluvatar-bi-v150-and-bi-v250-fabric. That record is a verified negative about a DIFFERENT, NEWER part whose vendor page publishes no specification section whatsoever. The pair together is the finding: Iluvatar's disclosure went backwards between generations.