NVIDIA NVLink 3.0

PER LINK, PER DIRECTION - NOW SOURCED TO A FIRST-PARTY NVIDIA DOCUMENT, 2026-10-03. The A100 datasheet (net2-nvidia-a100-datasheet) carries the figure in its Interconnect spec row: 'NVIDIA NVLink: 600GB/s' with footnote '** SXM4 GPUs via HGX A100 server boards', and the prose states 'NVIDIA NVLink in A100 delivers 2X higher throughput compared to the previous generation. When combined with NVIDIA NVSwitch, up to 16 A100 GPUs can be interconnected at up to 600 gigabytes per second (GB/sec)'. That confirms the 600 GB/s is the per-GPU BIDIRECTIONAL AGGREGATE across 12 links, not a per-direction rate - which is the specific claim this record was previously unable to make from Wikipedia. The per-direction aggregate is therefore 300 GB/s per GPU, and per link per direction is 600 / 12 / 2 = 25 GB/s, the recorded value. STRUCTURAL CROSS-CHECK, and this is the part worth remembering: NVIDIA's own NVLink architecture keeps the per-link rate at 25 GB/s per direction across NVLink 2 and NVLink 3, and generation 3 bought its 2x aggregate by doubling the LINK COUNT from 6 to 12, not the link rate - the V100's 300 GB/s aggregate is 6 links at 25, the A100's 600 is 12 links at 25 (link2-nvidia-ampere-architecture-whitepaper). So 'NVLink 3 is 50 GB/s' and 'NVLink 3 is 25 GB/s' are both wrong if quoted without saying per-direction or bidirectional; the 50 GB/s figure is the BIDIRECTIONAL per-link rate, and the 600 GB/s is the BIDIRECTIONAL per-GPU aggregate.

Direct point-to-point links between GPU pairs. All-to-all full mesh is only practical up to 8 GPUs; beyond that, NVSwitch is required to avoid partial connectivity.

None for direct-attached air-cooled parts. NVSwitch 3 provides an 8-GPU switched domain; without it an 8-GPU node is a partial mesh and the weakest link sets the all-reduce time for the whole group.

AUDIT 2026-10-03: status upgraded contested -> verified and confidence raised 0.7 -> 0.9. The record's only source was Wikipedia (kind 'review'); the authoritative public document, the A100 datasheet, has now been retrieved and confirms the 600 GB/s bidirectional per-GPU aggregate across 12 links, from which the recorded 25 GB/s per link per direction follows arithmetically. What Wikipedia was needed for - the sub-link structure of 4 differential pairs from NVLink 3 onward - remains secondary, but it no longer carries the bandwidth number, which was the contested part. HEADLINE CAPABILITY, the third required quantity for this generation, stated explicitly: NVLink 3 DOUBLED THE PER-GPU BIDIRECTIONAL AGGREGATE TO 600 GB/S BY DOUBLING THE LINK COUNT FROM 6 TO 12, holding the per-link rate flat at 25 GB/s per direction - 'The total number of links is increased to twelve in A100, versus 6 in V100, yielding 600 GB/sec total bandwidth versus 300 GB/sec for V100' (link2-nvidia-ampere-architecture-whitepaper). The secondary capability is the per-link SerDes improvement that made the doubling possible on the same die area: 'Third-generation NVLink has a data rate of 50 Gbit/sec per signal pair, nearly doubling the 25.78 Gbits/sec rate in V100', with half as many signal pairs per link as V100 - so NVIDIA raised the signalling rate per pair AND halved the pairs per link, holding the per-link rate constant and buying aggregate scale. For inference, the generation's practical significance is the first one where the fabric stops being the binding constraint on a node: 300 GB/s per direction per GPU against A100's 1.55 TB/s memory interface. PROVENANCE 2026-10-05: the 25 GB/s per link per direction is TRANSCRIBED VERBATIM ('provides 25 GB/second bandwidth in each direction'), while the 600 GB/s per-GPU figure is the datasheet's aggregate. Both directions of the same link pair therefore have different sources, which is worth knowing before treating the record as uniformly first-party. Foundational scale-up fabric: one coherent low-latency domain with hardware-managed direct memory access between GPUs. Inference consequence: tensor-parallel sharding wants the highest per-direction fabric rate available, because every layer boundary ships activations across the link; the bidirectional aggregate figure that dominates marketing is not what a single collective move sees. On a partial mesh an all-reduce that must route over a 2-hop path pays 2x the per-hop cost on that pair, so hierarchy-aware ring/tree algorithms beat flat ones. Direction convention note: NVIDIA states this as a bidirectional aggregate, the same convention as nvswitch-2, nvswitch-4 and nvlink-4 - which is the OPPOSITE of PCI-SIG's per-lane-per-direction convention on the pcie-* and cxl-* records, and that asymmetry is the single most common source of mismatched comparison in this repo. Both axes of the error are filed as gotcha w7n-nvlink-per-gpu-aggregate-vs-per-link-rate.