NVSwitch 3 (Hopper, H100/H200 - contested generation number)

PER GPU, PER DIRECTION, CONTESTED GENERATION NUMBER. BANDWIDTH IS NOT IN DISPUTE: 450 GB/s per direction is forced by the same 900 GB/s bidirectional per-GPU figure that nvswitch-4 carries, and NVIDIA's own Hopper developer blog states 'a system with eight NVIDIA H100 Tensor Core GPUs features 3.6 TB/s of bisection bandwidth and 450 GB/s of bandwidth for reduction operations' (net2-nvidia-nvswitch3-blog). 3.6 TB/s of bisection across 8 GPUs is 450 GB/s per GPU, and the blog's separate '450 GB/s of bandwidth for reduction operations' is the SHARP in-network-reduction rate - so 450 is both the per-GPU fabric rate and the reduction rate. WHAT IS CONTESTED IS THE NAME: NVIDIA's technical blog calls the Hopper switch 'third-generation NVIDIA NVSwitch', while the NVLink/NVLink Switch specification table labels the same part 'NVLink 4 Switch' paired with 'Fourth Generation' NVLink (link-nvlink-switch-spec). Both are first-party and both are in current NVIDIA materials. This is a pure vendor-naming disagreement with no numerical consequence, so per this repo's rules both labels are retained rather than one being chosen. Practical reading: NVIDIA numbered the switch generation separately from the link generation (Volta=1, Ampere=2, Hopper=3), while the spec table aligns switch generation with link generation (Hopper link 4 => '4 Switch'). See nvswitch-1 and nvswitch-2 for the same trap on other generations - on A100 the link is NVLink 3 but the switch is NVSwitch 2.

Switched, non-blocking all-to-all across the 8-GPU domain inside one server, as at NVSwitch 2 and 4. The Hopper generation's real additions are in-network compute and management rather than topology: SHARP in-network reduction and multicast, control-plane resilience, and the ability to run a partially populated rack.

Third-generation NVSwitch is where SHARP ARRIVES ON THE NVIDIA SCALE-UP SIDE. NVIDIA's Hopper architecture page states 'Third-Generation NVIDIA NVSwitch supports Scalable Hierarchical Aggregation and Reduction Protocol (SHARP) in-network computing, previously only available on InfiniBand, and provides a 2X increase in all-reduce throughput within eight H200 or H100 GPU servers compared to the previous-generation A100 Tensor Core GPU systems'. The 2x all-reduce claim is the directly relevant number for TP: SHARP moves the reduction into the switch, which attacks exactly the cost that docs/11-interconnect-decision.md measures. First-party port and throughput detail for this switch, from NVIDIA's GTC22 Hopper blog: 'Third-generation NVSwitch technology includes switches residing both inside and outside of nodes ... Each NVSwitch inside a node provides 64 ports of fourth-generation NVLink links to accelerate multi-GPU connectivity. Total switch throughput increases to 13.6 Tbits/sec from 7.2 Tbits/sec in the prior generation. New third-generation NVSwitch technology also provides hardware acceleration for collective operations with multicast and NVIDIA SHARP in-network reductions.' DIRECTION CAUTION ON THE 13.6 Tbit/s FIGURE: NVIDIA states it with NO direction qualifier, and it does not reconcile with 64 ports at the Gen4 per-port rate under either convention, so it is recorded verbatim and deliberately NOT converted into a bandwidth number here. What the blog does give first-party is the port count (64 NVLink ports per switch) and the 7.2 -> 13.6 Tbit/s step, and it distinguishes this in-node switch from the separate NVLink Switch SYSTEM object ('up to 32 nodes or 256 GPUs ... in a 2:1 tapered, fat tree topology ... 57.6 TB/sec of all-to-end bandwidth') - two different things that both appear under the name NVSwitch.

The Hopper-generation switch, added 2026-10-03 to complete the 1/2/3/4/5 ladder. It was genuinely missing, and its absence was actively misleading: the repo had nvswitch-2 (A100) and nvswitch-4 (H100) with no Hopper record, which invites a reader to conclude the switch was skipped between Ampere and Hopper. It was not. UNRESOLVED VENDOR NAMING, both first-party and both retained: NVIDIA's developer blog titles its Hopper switch discussion 'Upgrading Multi-GPU Interconnectivity with the Third-Generation NVIDIA NVSwitch', while NVIDIA's NVLink/NVLink Switch specification table labels the same Hopper switch 'NVLink 4 Switch' with the bandwidth row 'NVLink Switch GPU-to-GPU Bandwidth 900 GB/s' and 'Total Aggregate Bandwidth 7.2 TB/s' - identical to the NVSwitch 4 row. Two current first-party NVIDIA documents therefore disagree on whether this part is the 3rd or the 4th generation. No bandwidth impact: both give 900 GB/s bidirectional per GPU, and this record stores the halved 450 per direction. THE DECISION-RELEVANT FACT IS SHARP, not the name: NVIDIA's Hopper architecture page credits third-generation NVSwitch with 'a 2X increase in all-reduce throughput within eight H200 or H100 GPU servers compared to the previous-generation A100 systems' - the first NVIDIA scale-up part to do in-network reduction, previously an InfiniBand-only feature. That 2x is the same axis as the B* crossover in docs/11-interconnect-decision.md, and the two compose: H100's raw 450 GB/s per direction already puts the TP all-reduce crossover at B* ~3,318 on 7B geometry, so SHARP reduces a cost that is already negligible at typical serving batch, and its value shows up instead at high batch or high TP degree where B* is being approached. NVIDIA's separate inference blog (link-nvlink-nvswitch-inference-blog) reports up to 1.5x higher throughput for Llama 3.1 70B on H200 with NVSwitch versus point-to-point - the topology effect, which is separate from and smaller than the SHARP effect. AUDIT 2026-10-05: the record gains the GTC22 Hopper in-depth blog as a source (w7n-nvidia-hopper-architecture-in-depth-blog), which is NVIDIA's own prose statement of this switch's first-party port count and switch-throughput step - 64 NVLink ports per in-node switch, total switch throughput up to 13.6 Tbit/sec from 7.2 Tbit/sec - and which was not cited by any record before. It also surfaces a THIRD distinct object that the 2026-10-03 version of this record did not distinguish: the in-node third-generation NVSwitch (64 NVLink ports, this record), the second-level switches built from the same silicon that form the rack-scale NVLink Switch SYSTEM (up to 32 nodes or 256 GPUs, 2:1 tapered fat tree, 57.6 TB/sec), and the per-GPU-pair link bandwidth. Three quantities, two hardware objects, one brand name. The 13.6 Tbit/sec figure is carried verbatim into the switching field and explicitly not converted, because NVIDIA attaches no direction qualifier to it and it does not reconcile with 64 ports at the Gen4 per-port rate under either convention - the rule this repo follows is that an unlabelled figure is stored as published with its ambiguity named, never silently assigned a direction. DIRECTION AND SCOPE, restated for this record specifically because it is a switch and not a link: 450 GB/s is PER GPU PER DIRECTION, halved from NVIDIA's 'NVLink Switch GPU-to-GPU Bandwidth 900 GB/s', which is bidirectional and is per GPU PAIR. The link_count field on this record is 8 - the DOMAIN SIZE, not a per-GPU link count - so unlike an nvlink-* record you must not divide the aggregate by it. That asymmetry between the nvlink-* and nvswitch-* records is the third way to misread this family and is filed with the other two in gotcha w7n-nvlink-per-gpu-aggregate-vs-per-link-rate.