NVIDIA developer blog 'NVIDIA Hopper Architecture In-Depth' (H100 / GH100, GTC22)

First-party NVIDIA GTC22 technical blog on Hopper. Added 2026-10-05 because the nvlink-4 and nvswitch-3 records were sourcing the Hopper interconnect generation from the H100 product page and a later NVSwitch blog, while this document states the interconnect figures in NVIDIA's own prose and was not cited by any record. VERBATIM, H100 key feature summary, fourth-generation NVLink: 'Fourth-generation NVIDIA NVLink provides a 3x bandwidth increase on all-reduce operations and a 50% general bandwidth increase over the prior generation NVLink with 900 GB/sec total bandwidth for multi-GPU IO operating at 7x the bandwidth of PCIe Gen 5.' Three separate quantities in one sentence, and they must be kept apart: '3x bandwidth increase on all-reduce operations' is the collective-specific headline; '50% general bandwidth increase' is the general per-GPU change; '900 GB/sec total bandwidth for multi-GPU IO' is the per-GPU figure that the nvlink-4 record treats as a BIDIRECTIONAL AGGREGATE across 18 links. The word 'total' here is NVIDIA's own label for the aggregate convention. VERBATIM, third-generation NVSwitch: 'Third-generation NVSwitch technology includes switches residing both inside and outside of nodes to connect multiple GPUs in servers, clusters, and data center environments. Each NVSwitch inside a node provides 64 ports of fourth-generation NVLink links to accelerate multi-GPU connectivity. Total switch throughput increases to 13.6 Tbits/sec from 7.2 Tbits/sec in the prior generation. New third-generation NVSwitch technology also provides hardware acceleration for collective operations with multicast and NVIDIA SHARP in-network reductions.' This is the first-party source for NVSwitch 3's 64 NVLink ports and for the 7.2 -> 13.6 Tbits/sec switch-throughput step. NO DIRECTION CONVENTION IS STATED for the 13.6 Tbit/sec figure and it does not reconcile with 64 ports at the Gen4 per-port rate under either convention, so it is recorded verbatim in the switching field and deliberately NOT converted into a bandwidth number. VERBATIM, NVLink Switch System: 'New NVLink Switch System interconnect technology and new second-level NVLink Switches based on third-gen NVSwitch technology introduce address space isolation and protection, enabling up to 32 nodes or 256 GPUs to be connected over NVLink in a 2:1 tapered, fat tree topology. These connected nodes are capable of delivering 57.6 TB/sec of all-to-end bandwidth'. First-party for the rack-scale domain NVIDIA claims at this generation - note this is the NVLink Switch SYSTEM (multi-node, 256 GPUs), a different object from the in-node third-generation NVSwitch. MODEL BEHAVIOUR FOR THE DIRECTION GOTCHA, and it is the same double-printing discipline Intel uses on the Gaudi 3 sheet: 'PCIe Gen 5 provides 128 GB/sec total bandwidth (64 GB/sec in each direction) compared to 64 GB/sec total bandwidth (32GB/sec in each direction) in Gen 4 PCIe.' NVIDIA prints the aggregate AND the per-direction figure in the same sentence for PCIe. For the NVLink interconnect rows in the same document NVIDIA prints only 'total bandwidth' and never the per-direction half, which is why every NVLink record in this repo must halve it explicitly and say so. Also carries the GH100/H100 unit breakdown used by the accelerator records (8 GPCs, 72 TPCs, 144 SMs full die; 132 SMs SXM5, 114 PCIe; 60 MB L2 full die, 50 MB shipping; 6 HBM3 stacks full die, 5 shipping) and the FP16/FP8 Tensor Core table with the 'Effective TFLOPS / TOPS using the Sparsity feature' footnote that governs the halving rule. All performance figures on the page are labelled preliminary.