id
interconnect/ualink-200g-1-0
Bandwidth (GB/s, per link, unidirectional)
25
Bandwidth basis
PER LANE, PER DIRECTION - CORRECTED IN AUDIT 2026-10-03, THE UNIT ERROR. The consortium states '200G per lane' (link-ualink-specification-index), and 200G is 200 GIGABITS per second. The previous value of 200 in this GB/s field silently treated '200G' as 200 GIGABYTES per second, overstating the per-lane rate by 8x. Converted correctly: 200 Gb/s = 200 / 8 = 25 GB/s per lane per direction, which is the recorded value. THE 8x MATTERS: at 200 'GB/s' per lane, UALink would have looked roughly 4x faster than NVLink 4's 450 GB/s per direction per GPU on a per-lane comparison; at the correct 25 GB/s per lane it is exactly the SAME per-lane rate as NVLink 2/3/4, which is the actual and much more credible claim - UALink reuses IEEE 802.3 PAM4 SerDes, and NVLink 4 is 50 Gb/s per differential pair with 4 pairs per sub-link giving 25 GB/s per direction per link. link_count 16 remains the consortium's standard 16-lane scale-up port width and is flagged in notes as the weakest claim in this record; there is NO published x16 or per-GPU aggregate for UALink in any retrieved source, so none is recorded here and a per-pod aggregate must not be inferred from the lane rate alone without a vendor-confirmed port width. (A 16-lane port at 25 GB/s per lane would be 400 GB/s per direction, but that multiplication is this repo's arithmetic, not a consortium figure.)
Topology
Multi-layer fabric (UPLI protocol / transaction / data link / physical). Consortium-supported topologies: mesh and ring for small clusters of 4-16 nodes, torus for mid-scale, SWITCHED POD as the primary deployment model scaling to hundreds or thousands of accelerators, and direct-attach for small clusters. Complex ring and torus topologies are explicitly out of specification scope and need care to avoid deadlocks.
Switching
Switches are the primary scale-up model, as opposed to NVLink's NVSwitch which is a vendor-specific companion. Common 2.0 adds In-Network Compute, letting reduction traffic be processed between accelerators rather than only at endpoints.
notes
The open scale-up standard: an alternative to NVLink, positioned as deterministic, lossless, sub-microsecond round-trip, reusing commodity Ethernet PAM4 economics. Inference consequence and current status: this is a SPECIFICATION, not a shipping product line. The white paper states UALink 200G 1.0 was published April 2025 and that switch evaluation hardware is expected late 2026, with multiple vendors developing switches, retimers, connectors and transport engines. As of the access date there is no production silicon, so no measured inference number can reference UALink. Consortium reports 115+ member companies including AMD, Apple, AWS, Cisco, Google, Intel, Meta, Microsoft and Alibaba. Stated efficiency is 93% protocol payload over physical-layer capacity, 64-256 byte transactions, and a 57-bit physical address space supporting 128 PB directly addressable. The strategy significance is that a multi-vendor scale-up option removes NVIDIA's single-vendor hold on tensor parallelism, which is why it matters even with no silicon. AUDIT 2026-10-03: the per-lane value was corrected from 200 to 25 GB/s - the consortium says 200 GIGAbits per lane, and the old value read that as 200 GIGAbytes, an 8x overstatement that would have made a specification with no shipping silicon look 4x faster than NVLink 4. Corrected, UALink's 25 GB/s per lane per direction is level with NVLink 2/3/4 per link, which is the honest comparison and consistent with UALink's reuse of 802.3 PAM4 SerDes. Verification caveat: the 200 Gb/s per-lane rate and the 1,024 accelerator pod limit are consortium-stated; the port-width figure in link_count remains the weakest claim in this record and is not used to derive any aggregate.