UALink white paper (TASK Consultancy)

Technical overview: four-layer architecture (UPLI/TL/DL/PL), sub-microsecond round-trip latency, 64-256 byte transactions, 57-bit physical address space / 128 PB directly addressable, 93% bandwidth efficiency, 1024 endpoints. Supported topologies: mesh and ring for 4-16 nodes, torus for mid-scale, switched pod as the primary large-scale deployment, direct attach for small clusters. Reuses IEEE 802.3 PAM4 PHYs, cables, connectors and retimers. UALink 200G 1.0 published April 2025; switching evaluation hardware expected late 2026. Consortium has 115+ members.