GLM-4.7-Flash

head_dim FILLED = 256, and for MLA this is a DERIVED sum, not a config scalar: config has no head_dim key because there is no single head width. The query head is qk_nope_head_dim 192 + qk_rope_head_dim 64 = 256, and the value head is v_head_dim 256. Both halves are 256, so the record's single head_dim is well defined at 256 - but a reader should know it is a coincidence of this config, not a general MLA property, and that the KV cache (54,144 B/token) is computed from the 512-rank latent, NOT from this 256. The generation where Z.AI brought MLA back: config has kv_lora_rank 512, q_lora_rank 768, qk_nope_head_dim 192, qk_rope_head_dim 64, v_head_dim 256, and HF's Glm4MoeLiteAttention is explicitly documented 'Multi-headed Latent Attention (MLA) from Deepseek V2' with kv_a_proj_with_mqa and kv_b_proj. kv_cache_bytes_per_token = 47 layers x (kv_lora_rank 512 + qk_rope_head_dim 64) x 2 bytes = 47 x 576 x 2 = 54,144 B/token (52.9 KiB). The GQA formula does not apply. This is the fix for GLM-4.5's problem: versus GLM-4.5's 368 KiB/token at 32B active, this does 3B active in 52.9 KiB - a 7x KV reduction against a 32B-active model in the same family. Vendor calls it a 30B-A3B MoE; safetensors total 31.22B, our config arithmetic 31.2B. MoE: 64 routed + 1 shared, only 4 per token (lower than DeepSeek/GLM-4.5's 8), first_k_dense_replace 1. hidden 2048, moe_intermediate_size 1536, intermediate 10240. Context 202752, rope_theta 1000000. MIT. SERVICEABILITY JOIN (added 2026-10-03; the architecture x engine matrix this record was missing, with a citation per cell in docs/13-model-compatibility.md): FAMILY=mla. REQUIRED KERNEL CLASS: an MLA decode kernel. MLA is not a variant of the GQA kernel - the cache is a shared low-rank latent (d_c) plus a decoupled RoPE key, not per-head K/V, so an engine that lacks a dedicated MLA decode path cannot serve the class at all. SUPPORTED BY (cited): vLLM native rows DeepseekV2ForCausalLM, DeepseekV3ForCausalLM, DeepseekV32ForCausalLM, DeepseekV4ForCausalLM [[mdl2-vllm-supported-models-2026-10]]; TensorRT-LLM the same four rows plus GlmMoeDsaForCausalLM (GLM-5), Glm4MoeForCausalLM (GLM-4.5/4.6/4.7), KimiK3ForConditionalGeneration and KimiLinearForCausalLM [[mdl2-trtllm-supported-models]]; SGLang generative table names DeepSeek v1/v2/v3/R1 and Kimi K2 as supported [[mdl2-sglang-generative-models]]; llama.cpp reaches MLA through the DEEPSEEK2/DEEPSEEK32/DEEPSEEK4 arch entries, which are in its supports_sm_tensor == false list, i.e. no tensor-core matmul path for the attention itself [[mdl2-llamacpp-arch-class-registry]]; ik-llama-cpp records MLA as a feature that landed there first and was later upstreamed [[ik-llama-cpp]].ENGINE KERNEL CONSTRAINTS THAT CHANGE WHAT THE ENGINE MUST STORE (this is the important class of fact): (1) FlashInfer, which is SGLang's default attention backend and selectable in vLLM [[flashinfer]], is where the MLA decode kernels live, and they are instantiated per KV cache page-block size: gotcha-sm120-sparse-mla-block-size records vLLM computing compressed-layer pbs = block_size // compress_ratio (= 32 at block_size 64 for a ratio-2 layer) while FlashInfer's SM120 planner hard-codes _PAGE_BLOCK_SIZE = 64, so DeepSeek-V4.1-Flash will not start on 8x RTX PRO 6000 at TP8 at ANY global block size (64 gives pbs=32 and crashes; 128 gives 'No common block size'). Workaround is SM100 datacenter Blackwell or a FlashInfer planner change. (2) FlashMLA's 2026.09.30 release requires SM100/SM103 and CUDA >= 13.1, REMOVED Hopper support and removed V3/V3.2/V4.0, and supports ONLY FP8 and FP4 KV cache - unquantized bfloat16 KV is explicitly not supported [[kern-flashmla-github]]. So the kernel choice decides the KV CACHE FORMAT: to use that decode kernel the engine must store an FP8/FP4 latent with per-token inlined scales, and V4.1's layout is 528 bytes/token (512 of float8_e4m3 over all 512 dims - the 64 RoPE dims are quantized too, no bf16 part - plus 16 bytes of float8_e8m0 scales, one per 32 e4m3 values), with an fp4 variant at 288 bytes/token [[flashmla-decode-fp8-fp4-kv]]. A Hopper box therefore cannot take that kernel and an engine that only offers bf16 MLA KV cannot take it either. (3) Independent of the kernel: TRT-LLM's MLA rows carry two footnotes that constrain serving rather than correctness - chunked prefill for MLA only enables on SM90/SM100/SM103/SM107/SM120, and KV cache reuse for MLA only enables on SM90/100/103/107/120/121 in BF16/FP8 [[mdl2-trtllm-supported-models]]. (4) TRT-LLM states DeepSeek-V4 is Blackwell SM100+ only and Kimi K3 is SM100 family only, with a worked recipe split (DEP16 needs GB300-class per-GPU memory, TEP16 validated on GB200) [[mdl2-trtllm-supported-models]]. ISA CONSEQUENCE: at 68.6 KiB/token MLA moves the bottleneck off KV and onto weight streaming, so MLA-capable engines find their paged-attention machinery largely idle and their GQA-era cache-pressure tuning irrelevant [[mla-latent-attention]]. TRT-LLM covers GLM-4.7 via Glm4MoeForCausalLM (GLM-4.5, 4.6, 4.7) and 4.7-Flash separately via Glm4MoeLiteForCausalLM in vLLM's registry [[mdl2-trtllm-supported-models]] [[mdl2-vllm-supported-models-2026-10]]. Guided decoding for the Glm4Moe row is xgrammar-only, llguidance not working - a serving caveat unrelated to MLA but on the same row [[mdl2-trtllm-supported-models]].