GGUF IQ1_S (1.5625 bpw, non-linear 1-bit-ish with a 16-bit grid high plane)

CORRECTED 2026-10-04: 256 IS right here and the distinction matters. block_iq1_s is `{ ggml_half d; uint8_t qs[QK_K/8]; uint16_t qh[QK_K/32]; }` - ONE fp16 d for the whole 256-value super-block, no sub-block scales (the QK_K/32 loop in dequantize_row_iq1_s walks the high-index-bit plane, not a scale plane). 1.5625 bpw = 50 bytes / 256. SCHEMA MISMATCH: there is no ggml/iq* value in the quantization scheme enum, so this record uses the closest existing value 'gguf-q4_k_m' (or 'gguf-q2_k') and puts the true type in `name` and `bits`. Requested enum additions are listed in the task report. Weight-only by construction: activations are promoted to q8_K (an intermediate dot-product format, not a storage format) and the matmul runs at fp16/bf16, so native_support is deliberately EMPTY and the whole accelerator ecosystem is emulated_support. No accelerator has an i-quant or k-quant path in silicon. COMMON TO ALL IQ-QUANTS, verified from ggml/src/ggml-common.h: they use the QK_K = 256 super-block like the K-quants, but instead of a UNIFORM integer grid they quantize to indices into a per-block CODEBOOK of 256 learned non-uniform 4-bit values (the 'i' in i-quant is for the codebook grid / i-quant from the ik_llama.cpp lineage). The index lookup is table-driven at dequant time, which is why they compress better than K-quants at the same nominal bits and why they dequantize more slowly - the dot product needs a gather from the codebook. This is a real throughput trade, not a free win. BACKEND SITUATION, verified: the CUDA library shipped in llamafile releases is size-optimized and OMITS the IQ-quant kernels (IQ1_*, IQ2_*, IQ3_*, IQ4_*); offloading an IQ-quantized model to an NVIDIA GPU therefore leaves those layers on the CPU with correct output but no GPU acceleration (qlab2-llamafile-support-docs). The Metal and ROCm builds are NOT size-optimized and include full IQ-quant GPU support - so an RX 7900 XTX on ROCm/HIP is in a materially better IQ position than an RTX 4090 on a stock llamafile build. Vulkan has no dedicated IQ-quant path. Upstream llama.cpp has per-type dequant kernels; ik_llama.cpp additionally ships the Trellis family (IQ1_KT/IQ2_KT/IQ3_KT/IQ4_KT, integer-base trellis, CUDA PR 113 / Metal PR 475 / NEON PR 471 / CPU PR 441) and _R4/_R16 row-interleaved variants. IQ1_S is the smallest i-quant in the tree and the clearest case for the 'i-quant is not '1-bit' naming convention: qs[QK_K/8] = 32 bytes holds the LOW 8 bits of a grid index and qh[QK_K/32] = 16 bytes (as uint16_t) holds the HIGH 3 bits, so each element carries up to 11 index bits selecting from a large codebook, all under one fp16 scale per 256 values. 50 bytes / 256 = 1.5625 bpw, matching the '1.5625 bpw' comment. MIXTURE: LLAMA_FTYPE_MOSTLY_IQ1_S maps to GGML_TYPE_IQ1_S; for 8-expert (Mixtral) models IQ1_S is promoted to IQ2_XXS with the reasoning in the source, and the OUTPUT/tied-embedding tensor is forced to Q5_K for all i-quant ftypes (the IQ2_XXS/IQ2_XS/IQ3_XXS/IQ1_S/IQ2_S/IQ2_M/IQ1_M branch in llama_tensor_get_type_impl). In llama.cpp's own CPU table IQ1_S is the joint-fastest text-generation type measured at 79.73 t/s on Llama-3.1-8B, ahead of IQ2_XXS at 79.86 only by noise. SCHEME RECLASSIFIED (parent agent, 2026-10-03): scheme was 'gguf-q2_k' (a proxy recorded while the enum lacked a legal value) and is now 'gguf-iq1-s'. NATIVE_SUPPORT CLASSIFIED 2026-10-04: this field is still [] and that is CORRECT, but the empty list used to be ambiguous between three different states and now is not. Reason class on this record: LLAMA.CPP INTEGER STORAGE TYPE, SO STRUCTURALLY ABSENT. Every GGUF type here is a packed integer block format read by a dequant kernel (dequantize_row_*) and then executed as FP16; ggml publishes no int4 or sub-8-bit tensor-core path that consumes these blocks directly. The llama.cpp CUDA and Vulkan backends both run these formats by dequantizing. Consequence for a reader: nothing further to verify - and note the contrast with nvfp4/mxfp4/mxfp8 in this repo, which ARE hardware formats on Blackwell and carry populated native_support lists, so '4-bit' alone does not predict this field. The full statement of the three-way distinction, and the worked list of all 72 empty records by class, is in gotcha quant-native-support-empty-means-three-different-things. Rule of thumb for this field everywhere in the repo: if the bits field carries an 'a16', or the scheme is KV-cache-only or a llama.cpp integer storage type, an empty native_support is a DEFINITION and needs no verification; only a W4A4/W8A8/sub-8-bit format with research kernels can have an empty list that is a real finding.