GGUF IQ4_NL (non-linear 4-bit, 32-value blocks, QK4_NL)

CORRECTED 2026-10-04: was 256. QK4_NL = 32 and block_iq4_nl is `{ ggml_half d; uint8_t qs[QK4_NL/2]; }` with NO sub-block scale plane at all - dequantize_row_iq4_nl applies the single fp16 d across all 32 values. This is the one GGUF type where 'block size' and 'scale group' coincide at 32 and there is no 256 super-block at all; the 256 was inherited from the K-quant convention. SCHEMA MISMATCH: there is no ggml/iq* value in the quantization scheme enum, so this record uses the closest existing value 'gguf-q4_k_m' (or 'gguf-q2_k') and puts the true type in `name` and `bits`. Requested enum additions are listed in the task report. Weight-only by construction: activations are promoted to q8_K (an intermediate dot-product format, not a storage format) and the matmul runs at fp16/bf16, so native_support is deliberately EMPTY and the whole accelerator ecosystem is emulated_support. No accelerator has an i-quant or k-quant path in silicon. COMMON TO ALL IQ-QUANTS, verified from ggml/src/ggml-common.h: they use the QK_K = 256 super-block like the K-quants, but instead of a UNIFORM integer grid they quantize to indices into a per-block CODEBOOK of 256 learned non-uniform 4-bit values (the 'i' in i-quant is for the codebook grid / i-quant from the ik_llama.cpp lineage). The index lookup is table-driven at dequant time, which is why they compress better than K-quants at the same nominal bits and why they dequantize more slowly - the dot product needs a gather from the codebook. This is a real throughput trade, not a free win. BACKEND SITUATION, verified: the CUDA library shipped in llamafile releases is size-optimized and OMITS the IQ-quant kernels (IQ1_*, IQ2_*, IQ3_*, IQ4_*); offloading an IQ-quantized model to an NVIDIA GPU therefore leaves those layers on the CPU with correct output but no GPU acceleration (qlab2-llamafile-support-docs). The Metal and ROCm builds are NOT size-optimized and include full IQ-quant GPU support - so an RX 7900 XTX on ROCm/HIP is in a materially better IQ position than an RTX 4090 on a stock llamafile build. Vulkan has no dedicated IQ-quant path. Upstream llama.cpp has per-type dequant kernels; ik_llama.cpp additionally ships the Trellis family (IQ1_KT/IQ2_KT/IQ3_KT/IQ4_KT, integer-base trellis, CUDA PR 113 / Metal PR 475 / NEON PR 471 / CPU PR 441) and _R4/_R16 row-interleaved variants. IQ4_NL IS THE EXCEPTION TO THE 256 SUPER-BLOCK: it is the only i-quant with QK4_NL = 32, i.e. a 32-value block with a single fp16 scale and 4-bit codebook indices - structurally almost identical to legacy q4_0 except that the 16 levels are non-uniform codebook entries rather than a uniform 0-15 grid. It is the cheapest i-quant to dequantize (small block, no extra scale plane) and is the i-quant most likely to have a fast GPU path. MIXTURE: llama-quant.cpp maps LLAMA_FTYPE_MOSTLY_IQ4_NL to GGML_TYPE_IQ4_NL, and the base weight is promoted to Q5_K in the first n_layer/8 ffn_down layers ONLY when no imatrix is present (the condition is `i_layer < n_layer/8 && ftype == IQ4_NL && !qs.has_imatrix`) - i.e. with an imatrix the schedule is left alone, which is a concrete, verifiable example of imatrix changing the type assignment and not just the rounding. attn_v is promoted to Q5_K when n_gqa >= 4, and to Q8_0 on Mixtral-style 8-expert models. Practically, IQ4_NL is the i-quant to pick if you want i-quant quality without losing GPU acceleration. SCHEME RECLASSIFIED (parent agent, 2026-10-03): scheme was 'gguf-q4_k_m' (a proxy recorded while the enum lacked a legal value) and is now 'gguf-iq4-nl'. NATIVE_SUPPORT CLASSIFIED 2026-10-04: this field is still [] and that is CORRECT, but the empty list used to be ambiguous between three different states and now is not. Reason class on this record: LLAMA.CPP INTEGER STORAGE TYPE, SO STRUCTURALLY ABSENT. Every GGUF type here is a packed integer block format read by a dequant kernel (dequantize_row_*) and then executed as FP16; ggml publishes no int4 or sub-8-bit tensor-core path that consumes these blocks directly. The llama.cpp CUDA and Vulkan backends both run these formats by dequantizing. Consequence for a reader: nothing further to verify - and note the contrast with nvfp4/mxfp4/mxfp8 in this repo, which ARE hardware formats on Blackwell and carry populated native_support lists, so '4-bit' alone does not predict this field. The full statement of the three-way distinction, and the worked list of all 72 empty records by class, is in gotcha quant-native-support-empty-means-three-different-things. Rule of thumb for this field everywhere in the repo: if the bits field carries an 'a16', or the scheme is KV-cache-only or a llama.cpp integer storage type, an empty native_support is a DEFINITION and needs no verification; only a W4A4/W8A8/sub-8-bit format with research kernels can have an empty list that is a real finding.