Qualcomm Cloud AI 100 announcement deck (hardware architecture slide)

16-slide official announcement deck. The 'Hardware Architecture' slide is the primary source for the SoC-level detail that the product brief omits, and reads verbatim: 'Up to 400 TOPS', 'Power: DM.2e @ 15W, DM.2 at 25W, PCIe/HHHL @ 75W', 'AI Core (AIC) - Up to 16 cores', 'Precision - INT8, INT16, FP16, FP32', 'On-die SRAM - Up to 144 MB', '4x64 LPDDR4x (2.1GHz) with inline ECC', 'Up to 32GB on card DRAM', 'PCIe Gen 3/4 - Up to 8 lanes'. THIS IS THE PROOF that the family supports FP16 and FP32 as execution precisions and therefore that the absence of a TFLOPS figure is a disclosure gap rather than an architectural one. The '4x64 LPDDR4x (2.1GHz)' line is the only primary hint of a per-pin data rate (2.1 GHz effective) but it is a channel count and a speed grade, NOT a bus width, so 137 GB/s still cannot be attributed to a specific bus - 137 GB/s x 8 / 2.1 GHz = 522 bit, which is not a standard LPDDR4X width, confirming the brief is quoting a system-level figure. An earlier slide also gives the family-level '>50 TOPS' and '200 TOPS' generation markers.