Qualcomm Cloud AI 100 (family: HHHL-Pro / HHHL-Std / HHHL-Lite / Dual M.2 / Dual M.2e)

ADDED 2026-10-03 to close a real gap: the id 'qualcomm-ai100' was referenced by flops-custom-kernel-launch-overhead (affected_by_hardware) with no accelerator record in the repo. Qualcomm has since renamed and superseded this line (AI200, and then AI250), and its own product page for AI100 no longer serves content, so this record is built from the two official Qualcomm PDFs that remain live: the Cloud AI 100 product brief and the announcement deck. THE MOST IMPORTANT THING ABOUT THIS RECORD IS THE EMPTY flops ARRAY, and it is deliberately empty. Qualcomm publishes this family's throughput as 'ML Capacity (INT8)' in TOPS - up to 400 TOPS on the HHHL-Pro, 350 on HHHL-Std, 137 on HHHL-Lite, 200 on Dual M.2, 70 on Dual M.2e - and publishes NO TFLOPS or FP16 figure anywhere in the product brief, the announcement deck, or the current product page. The schema's flops array is TFLOPS-keyed, so there is no honest way to express 400 TOPS-INT8 in it, and converting TOPS-INT8 into an FP16 TFLOPS number would manufacture a figure no Qualcomm document endorses. Qualcomm's announcement-deck Hardware Architecture slide does prove the silicon supports FP16 and FP32 as execution precisions ('Precision - INT8, INT16, FP16, FP32', 'AI Core (AIC) - Up to 16 cores'), so this is a disclosure gap, not an architectural one - but the number itself remains unpublished and status is therefore draft rather than verified. If a future Qualcomm source publishes an FP16 rate, that row should be added with the source, not inferred. WHY THE INT8-NATIVE FRAMING IS THE PART THAT MATTERS: this is the one accelerator family in this repo whose vendor headline metric is INT8 TOPS rather than FP16 TFLOPS, and it is deliberate on Qualcomm's side - the AI core is 'a scalar 4-way VLIW architecture that includes vector/tensor units and lower precision to enable high-performance inference'. Qualcomm ran MLPerf Inference on this card (their own decks: MLPerf v3.0 and v3.1 Cloud AI 100 submissions). EDGE/MOBILE POSITIONING: Qualcomm's AI100/AI200 accelerators are primarily designed for edge and mobile inference, NOT datacenter LLM serving. The HHHL and M.2 form factors, LPDDR4X memory, 75W TDP, and INT8-native architecture all point to a low-power edge inference use case. These are not competitors to datacenter GPUs or Trainium for LLM serving - they are for vision, NLP, and recommendation models at the edge. The AI200 (Cloud AI 100 Ultra) with 128GB LPDDR4X at 548 GB/s is the closest to a datacenter part, but even that is a capacity play for holding models resident rather than a throughput play. Qualcomm's AI250 (announced 2025) is the successor targeting datacenter-scale inference with HBM and higher bandwidth. a 2.0/2.1 inference-performance deck), so the claim is benchmarked rather than theoretical. The practical consequence for anyone comparing this to a GPU: a TOPS-INT8 number and a TFLOPS-FP16 number are not comparable, and the two large TOPS figures that circulate for Qualcomm parts are per-CARD, not per-system. Also unpublished, and left null for the same reason: process node appears on the announcement deck only as a narrative 'using 7nm' (process_nm 7 reflects that, and is also corroborated by the Hot Chips 33 presentation), no bus width, no clock, no ECC overhead figure (the deck does say '4x64 LPDDR4x (2.1GHz) with inline ECC' - inline ECC is a data-integrity feature here, not the workstation-style capacity-tax ECC found on the Radeon PRO parts). On-die SRAM is published and unusual for this class: up to 144 MB on the HHHL-Pro, which is a genuine differentiator for inference because it is fast on-package scratch rather than off-package DRAM. TDP is per-card and per-form-factor (15-25 W M.2, 35/45/55 W configurable HHHL-Lite, 75 W HHHL), which is the actual selling point - this is a power-capped inference part, not a training part, and Qualcomm positions it for cloud and edge inference rather than training. SOFTWARE, because it decides whether any of this is reachable: Qualcomm ships a parallelizing compiler and platform SDK, and the stack is available through Qualcomm AI Hub (aihub.qualcomm.com) with published ONNX and PyTorch workflows. A vLLM maintainer noted to ServeTheHome that NVIDIA likely has more software headcount, i.e. the ecosystem gap is the real adoption risk. Scale-out is over a PCIe switch with peer-to-peer capability (again per the Hot Chips 33 presentation) rather than a proprietary accelerator fabric - NVLink is explicitly not relevant here. INTERCONNECT FILLED 2026-10-04: this record had NO interconnect key at all; it now reads ['pcie-gen4'], from the vendor's own spec table ('the Cloud AI 100 product brief's 'Host Interface' row, which prints 'PCIe Gen 4 8 lanes' for the HHHL/HHHL-Pro form factors and 'PCIe Gen 3 4 lanes' x2 for the Dual M.2 / Dual M.2e variants'). Note the backward-compatibility clause is part of the vendor's published value and is why the field records the HIGHEST supported generation rather than the lane count: the interconnect schema has no lane-count or backward-compatibility field, so 'pcie-gen4' on a '4.0 Ready (x16) with 3.0 Backward Compatibility' card means 'Gen 4 is what this part supports at full rate', not 'Gen 3 cards cannot be used'. Scale-up fabric: none. Qualcomm publishes no scale-up fabric for this family, and the dual-M.2 SKUs are independent cards rather than a linked pair - so the host interface really is the whole of it. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes no memory-bus width for this part, and none was back-computed from the published bandwidth. This is the correct state of the field for a part with no vendor width figure.