Qualcomm Cloud AI 100 product brief (five PCIe/M.2 form factors, spec table)

Single-page official product brief, fetched and text-extracted in full on 2026-10-03. Its five-column table is the primary source for the whole Cloud AI 100 family and is the ONLY vendor-published per-SKU spec table for these parts. Rows are: Power (TDP) 75 W (HHHL-Pro) / 75 W (HHHL-Std) / 35, 45, 55 W configurable (HHHL-Lite) / 15-25 W (Dual M.2) / 15-25 W (Dual M.2e); ML Capacity (INT8) Up to 400 TOPS / Up to 350 TOPS / Up to 137 TOPS / Up to 200 TOPS / Up to 70 TOPS; On-Die SRAM 144 MB / 126 MB / 81 MB / 126 MB / 81 MB; On-Card DRAM '32 GB LPR4x 137 GB/s' / '16 GB LPR4x 137 GB/s' / '16 GB LPR4x 137 GB/s' / '16 GB LPR4x 137 GB/s' / '8 GB LPR4x 68 GB/s'; Host Interface 'PCIe Gen 4 8 lanes' x3 / 'PCIe Gen 3 4 lanes' x2. CRITICAL CONVENTIONS: (a) Qualcomm publishes ML capacity in TOPS at INT8 and publishes NO TFLOPS/FP16 figure anywhere in this brief or on the product page, so no FP16/FP32 throughput may be recorded for this family - it is not published. (b) There is no memory_bus_bit row at all; the DRAM figures are capacity plus a GB/s bandwidth in the same cell, so bus width is NOT published and must stay null rather than be back-computed. (c) There is no process_nm row. (d) There is no sparsity statement anywhere in the brief, so Qualcomm makes NO dense-or-sparse claim for the Cloud AI 100 family, and no TOPS figure should be flagged sparse.