inference/research
verifiedhigh · 0.95updated 2026-10-04

Cloud TPU system architecture

spec-sheet

Fields

id
sources/alt-tpu-system-arch
URL
https://cloud.google.com/tpu/docs/system-architecture
Publisher
Google Cloud
Kind
spec-sheet
Published
2026-10-02
Accessed
2026-10-04
notes
Systolic array MXU sizes (256x256 for v6e+, 128x128 prior), 16K MACs per cycle per MXU, bf16 inputs with fp32 accumulation, SparseCore for embedding/LEM, ICI resiliency, 2D/3D torus topologies.

Notes

Systolic array MXU sizes (256x256 for v6e+, 128x128 prior), 16K MACs per cycle per MXU, bf16 inputs with fp32 accumulation, SparseCore for embedding/LEM, ICI resiliency, 2D/3D torus topologies.

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