id
interconnect/w7c-google-tpu-ici-tpu7x
Bandwidth (GB/s, per link, unidirectional)
600
Bandwidth basis
PER CHIP, PER DIRECTION, FROM THE BIDIRECTIONAL PER-CHIP ROW (1200 GB/s per direction). The TPU7x page's comparison table publishes 'Bidirectional inter-chip interconnect (ICI) bandwidth per chip (GBps) 1200' for TPU7x, identical to v5p's published 1200 and higher than v6e's 800 and v5e's 400. Two cautions. (1) THE SAME PAGE ALSO PUBLISHES A CONFLICTING-LOOKING FIGURE: 'It has bi-directional bandwidth of 200 GBps per axis for communication between chips within a pod.' 200 GBps per axis is a PER-AXIS figure for a 3D torus with three axes, so 3 x 200 = 600 GBps bidirectional per chip, which does NOT equal the 1200 GBps per chip of the comparison table - the two are a factor of 2 apart and Google does not reconcile them on the page. Per AGENTS.md's handling of disagreement, BOTH published values are kept and the record status is 'contested' rather than resolved by preference: the typed value carries the comparison-table row (per-direction half of 1200 GBps = 600 GB/s per direction per chip) and the per-axis figure is preserved in notes with its arithmetic, because the two cannot both be right and the source does not say which is. A reader who halves the 200 GBps per axis instead gets 100 GB/s per direction per chip, or 300 GB/s per direction across three axes - a 2x spread against the typed value. No third-party source has been consulted to break the tie. (2) Google writes 'GBps' (gigabytes) for these rows and 'Gbps' (gigabits) for the DCN row, in the same table. No ICI port count is published for TPU7x, so no per-port figure is derived.
Topology
3D TORUS, and TPU7x is the generation where the topology statement is doubled in the source: 'TPU7x chips have a direct connection to the nearest neighboring chips in 3 dimensions, resulting in a 3D mesh of networking connections' AND 'TPU7x chips have a 3D torus interconnect topology. This topology allows slices to scale up to 9216 chips.' So mesh-of-neighbours and torus are both stated for the same part - the mesh describes the physical adjacency, the torus the configured pattern, and unlike v4 Google does NOT publish a shape condition under which TPU7x gets a mesh instead of a torus. 9216-chip pod, slices built from 4x4x4 'cubes' above 64 chips, and the published shape table tops out at 8x16x16 = 2048 chips, 512 hosts, 32 cubes - SO AGAIN POD SIZE AND MAXIMUM SINGLE SLICE DIFFER, 9216 chips per pod against 2048 chips in the largest documented slice shape. TWISTED TOPOLOGY IS NOT MENTIONED on the TPU7x page; Google documents twisted topologies for v4 and v5p only, and the ICI-resiliency section on the system-architecture page names v4, v5p and TPU7x as the generations with resiliency enabled by default for slices of one cube or larger.
Switching
ICI is the scale-up fabric and the scale-up domain is the 9216-chip POD - the largest scale-up domain of any generation in this set. Google's documented boundary is ICI versus DCN, not 'scale-up'/'scale-out': ICI is 'high speed, low latency internal links that connect TPUs within a TPU Pod'; cross-slice traffic goes 'by transferring data to CPUs (hosts) which in turn transmit the data over the data-center network (DCN)', 'a higher latency, lower-throughput network (when compared with ICI)'. The booleans are this repo's mapping of that boundary. SCALE-OUT AS DOCUMENTED, TPU7x: 'Data center network (DCN) bandwidth per chip (Gbps) 100' in the comparison table, where v5p is 50 and v6e is 100 - direction is NOT stated, so it is recorded as published and flagged unstated. NO PER-HOST NIC CONFIGURATION IS PUBLISHED for TPU7x, unlike v5e (2 x 100 Gbps) and v6e (4 x 200 Gbps). HOST PACKING: 4 chips per TPU7x VM, and 'All TPU7x slices use full-host, 4-chip VMs', so the 9216-chip pod is 2304 VMs. CHIET-LEVEL SCALE-UP, WHICH IS A DIFFERENT FABRIC: the two chiplets inside one TPU7x chip are joined by a die-to-die interface that Google states is 'six times faster than a 1D inter-chip interconnect (ICI) link', and inter-chiplet communication is handled with collective operations. That D2D link is a scale-up path that is not ICI and is not in the data-centre network, so a reader who counts only ICI links understates the fabric by a factor of six on the path that matters most for a single chip.
notes
The generation with the most documentation traps, recorded because each one would otherwise be copied forward. (1) THE 1200-vs-600 PER-CHIP DISCREPANCY described in bandwidth_basis: the comparison table says 1200 GBps bidirectional per chip while the configurations section says 200 GBps bidirectional per axis, and a 3-axis torus at 200 GBps per axis totals 600 GBps. Unreconciled by Google; both figures are preserved here. (2) POD VERSUS SLICE: 9216 chips per pod against a 2048-chip largest documented slice shape. (3) CHIPS PER CHIP: TPU7x is dual-chiplet, so JAX exposes each chip as TWO devices and adds a fourth dimension to the topology tuple to distinguish chiplets - 'a departure from the unified memory space of the MegaCore architecture used in previous generations (TPU v4 and v5p)', where each chiplet has 96 GB of its own HBM and the pair totals 192 GB. Any model-fit arithmetic that divides a 192 GB figure by a device count is wrong by 2x on TPU7x. (4) GOOGLE'S OWN COMPARISON TABLE AND THE V6E PAGE DISAGREE ON DCN PER CHIP: the TPU7x page lists v6e DCN at 100 Gbps per chip, while the v6e page publishes per-host NICs (4 x 200 Gbps) and 25.6 Tbps per pod for a 256-chip pod at 8 chips per host - 25.6 Tbps / 256 chips = 100 Gbps per chip, so the two agree once pod arithmetic is done, which is a useful cross-check that the v5e equivalent (6.4 Tbps / 256 chips = 25 Gbps per chip) does NOT match any per-chip figure Google publishes for v5e, because v5e's page has no DCN-per-chip row at all. Per-pod ICI aggregate bandwidth, per-pod all-reduce and per-pod bisection are NOT published for TPU7x; the 1200 GBps per chip and the 9216-chip pod size are the whole of what the page gives, and no pod-level collective figure is invented here. Sources: alt-tpu7x-ironwood for every TPU7x figure including the per-axis bandwidth, the 9216-chip pod, the dual-chiplet D2D ratio and the 4-chip VM; w7c-google-tpu-multislice-overview for the ICI/DCN definitions; asic-tpu-v6e-specs and asic-tpu-v5e-specs for the cross-generation DCN comparison.