Horizon Robotics Journey 5 (J5) — developer documentation overview

Fields

id

sources/cn-horizon-journey5

URL

https://developer.d-robotics.cc/api/v1/fileData/horizon_j5_open_explorer_en_doc/oe_mapper/source/appendix/j5_introduction.html

Publisher

Horizon Robotics (地平线)

Kind

spec-sheet

Accessed

2026-10-03

notes

PRIMARY VENDOR SOURCE (Horizon developer documentation). Journey 5 (J5) is an AD-specific algorithm processor launched in 2021. Computing power: 8-core Cortex-A55 CPU, dual-core Vision P6 DSP (0.67 TOPS), dual-core BPU with Bayes architecture providing 128 TOPS. Memory: 64-bit LPDDR4/4X. ISP: two modules each supporting 2x4k/8M@30fps. Interfaces: 4x 2.5G MIPI CSI RX, 2x 2.5G MIPI CSI TX, 1x PCIe Gen3 2-lane, 2x 1Gb Ethernet (one with TSN), 4x CAN-FD. ASIL-B functional safety certified (ISO 26262). The BPU is designed for CNN-based perception workloads. Journey 5 was the first Horizon generation optimised for Transformers rather than CNNs. Multi-chip configurations reach up to ~1,024 TOPS for L4 autonomous driving.

Notes

PRIMARY VENDOR SOURCE (Horizon developer documentation). Journey 5 (J5) is an AD-specific algorithm processor launched in 2021. Computing power: 8-core Cortex-A55 CPU, dual-core Vision P6 DSP (0.67 TOPS), dual-core BPU with Bayes architecture providing 128 TOPS. Memory: 64-bit LPDDR4/4X. ISP: two modules each supporting 2x4k/8M@30fps. Interfaces: 4x 2.5G MIPI CSI RX, 2x 2.5G MIPI CSI TX, 1x PCIe Gen3 2-lane, 2x 1Gb Ethernet (one with TSN), 4x CAN-FD. ASIL-B functional safety certified (ISO 26262). The BPU is designed for CNN-based perception workloads. Journey 5 was the first Horizon generation optimised for Transformers rather than CNNs. Multi-chip configurations reach up to ~1,024 TOPS for L4 autonomous driving.

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