inference/research
verifiedmedium · 0.80updated 2026-10-03

Horizon Robotics Journey 5 (J5) automotive AI SoC

asic-other BPU 3.0 Bayes (dual-core) 2021

Fields

id
accelerators/horizon-journey-5
Vendor
asic-other
Architecture
BPU 3.0 Bayes (dual-core)
Release year
2021
Process (nm)
16
Form factors
socs
Memory type
lpddr4
Memory bus (bit)
64
Bandwidth basis
None available. The Horizon developer documentation states 'Support 64bit LPDDR4/4X memory' but publishes no bandwidth figure. The Journey 5's memory bandwidth is not stated in any source located.
Peak FLOPS
precisionint8tflops128denseyesvendor_claimyessource_idcn-horizon-journey5basisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for Horizon Robotics Journey 5 (J5) automotive AI SoC (source of record: 'Horizon Robotics Journey 5 (J5) — developer documentation overview', kind: spec-sheet). Recorded dense:true as printed.
Unified memory
no
Consumer part
no
notes
THE HIERARCHY POINT: Journey 5 is an automotive AI SoC, not a datacenter accelerator, and is included in this repo for completeness of the Chinese domestic AI accelerator landscape. It is NOT a plausible source of LLM inference hardware. VENDOR-PUBLISHED SPECIFICATIONS (Horizon developer documentation, primary source): 128 TOPS from dual-core BPU with Bayes architecture, 8-core Cortex-A55 CPU, dual-core Vision P6 DSP (0.67 TOPS), 64-bit LPDDR4/4X memory, PCIe Gen3 2-lane, 2x 2.5G MIPI CSI RX, 2x 2.5G MIPI CSI TX, 2x 1Gb Ethernet (one with TSN), ASIL-B functional safety certified (ISO 26262). The BPU is designed for CNN-based perception workloads. Journey 5 was the first Horizon generation optimised for Transformers rather than CNNs. The part is significant in the automotive AI market — Horizon shipped on navigate-on-autopilot vehicles in China at a reported 49% share of the Chinese self-driving chip market in 2023 — but its 128 TOPS INT8 on 16nm with LPDDR4 is not comparable to datacenter parts. Multi-chip configurations reach up to ~1,024 TOPS for L4 autonomous driving. Vendor is 'asic-other' because 'horizon' is not in the schema enum.

Notes

THE HIERARCHY POINT: Journey 5 is an automotive AI SoC, not a datacenter accelerator, and is included in this repo for completeness of the Chinese domestic AI accelerator landscape. It is NOT a plausible source of LLM inference hardware. VENDOR-PUBLISHED SPECIFICATIONS (Horizon developer documentation, primary source): 128 TOPS from dual-core BPU with Bayes architecture, 8-core Cortex-A55 CPU, dual-core Vision P6 DSP (0.67 TOPS), 64-bit LPDDR4/4X memory, PCIe Gen3 2-lane, 2x 2.5G MIPI CSI RX, 2x 2.5G MIPI CSI TX, 2x 1Gb Ethernet (one with TSN), ASIL-B functional safety certified (ISO 26262). The BPU is designed for CNN-based perception workloads. Journey 5 was the first Horizon generation optimised for Transformers rather than CNNs. The part is significant in the automotive AI market — Horizon shipped on navigate-on-autopilot vehicles in China at a reported 49% share of the Chinese self-driving chip market in 2023 — but its 128 TOPS INT8 on 16nm with LPDDR4 is not comparable to datacenter parts. Multi-chip configurations reach up to ~1,024 TOPS for L4 autonomous driving. Vendor is 'asic-other' because 'horizon' is not in the schema enum.

Cross-references

Interconnect (1)