Iluvatar CoreX Zhikai 100 / 50 (MR-V100 / MR-V50) inference accelerator card product page
spec-sheet
Fields
id
sources/cn-iluvatar-zhikai100Publisher
Iluvatar CoreX (天数智芯)
Kind
spec-sheet
Accessed
2026-10-03
notes
PRIMARY VENDOR SOURCE, and the most spec-dense Chinese accelerator page found in this exercise - note that it publishes memory capacity, TDP, form factor and bus generation but still NO compute throughput. MR-V100 (智铠100): 32 GB HBM2E, 150 W, full-height full-length single-slot PCIe, Gen4 x16, FP32/FP16/INT8 mixed inference, up to 128x 1080p30 H.264 decode. MR-V50 (智铠50): 16 GB HBM2E, 75 W, half-height half-length single-slot. Released December 2022 on Iluvatar's second-generation general-GPU architecture. Vendor claims 2-3x real-world performance vs mainstream parts, CUDA-ecosystem compatibility, and 50%+ reduction in migration time.
Notes
PRIMARY VENDOR SOURCE, and the most spec-dense Chinese accelerator page found in this exercise - note that it publishes memory capacity, TDP, form factor and bus generation but still NO compute throughput. MR-V100 (智铠100): 32 GB HBM2E, 150 W, full-height full-length single-slot PCIe, Gen4 x16, FP32/FP16/INT8 mixed inference, up to 128x 1080p30 H.264 decode. MR-V50 (智铠50): 16 GB HBM2E, 75 W, half-height half-length single-slot. Released December 2022 on Iluvatar's second-generation general-GPU architecture. Vendor claims 2-3x real-world performance vs mainstream parts, CUDA-ecosystem compatibility, and 50%+ reduction in migration time.
Cross-references
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