inference/research
draftlow · 0.50updated 2026-10-05

Iluvatar CoreX MR-V100 (Zhikai 100) HBM inference card

asic-other Iluvatar general GPU (2nd gen) 2022
This record is a draft. Not yet verified. Provisional. Treat every number on this page as provisional.

Fields

id
accelerators/iluvatar-mr-v100-zhikai100
Vendor
asic-other
Architecture
Iluvatar general GPU (2nd gen)
Release year
2022
Form factors
pcie
VRAM (GB)
32
Memory type
hbm2e
Bandwidth basis
None available, verified. Iluvatar publishes memory TYPE and CAPACITY on this card - '32 GB HBM2E' for the MR-V100, '16 GB HBM2E' for the MR-V50 - and publishes NO bandwidth figure, no bus width and no pin rate. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. Note the contrast with the BI-V100, where the vendor prints the same 64 GB/s figure for host and device links and it is therefore an interconnect number, not memory bandwidth; nothing on this page offers a memory bandwidth at all. Sources cn-iluvatar-zhikai100 and w5a-iluvatar-bi-v100-vendor-says-32gb-dram-hbm2 (recorded for the split).
TDP (W)
150
Unified memory
no
Consumer part
no
notes
CREATED BY THE SPLIT of iluvatar-bi-v100-mr-v100 on 2026-10-05, which held BI-V100 and MR-V100 in one record with a single memory_type. The two differ in memory technology (HBM2 vs HBM2E), power (250 W vs 150 W), slot width (dual vs single), role (training vs inference) and release year (2021 vs 2022), and the schema holds one memory_type per record, so a single record could not state either part correctly. WHY THE SPLIT IS WORTH MAKING RATHER THAN ANNOTATING: this card is the reason Iluvatar is in this repo at all. It ships HBM on an INFERENCE-ONLY card. The 产品规格 table, verbatim: '内存 | 16 GB HBM2E' (智铠50加速卡 MR-V50, '半长半高单槽 PCle 卡', '板级功耗 75W') and '32 GB HBM2E' (智铠100加速卡 MR-V100, '全长全高单槽 PCle', '板级功耗 150W'), interface 'PCle Gen4.0 X 16 lane'. Every other Chinese inference part in this repo is LPDDR - MLU370 at 307 GB/s, Ascend 310P at 204.8 GB/s - and even Moore Threads' S4000 is GDDR6, not HBM. HBM2E at inference power and inference pricing is a genuinely different proposition. NO COMPUTE FIGURE, verified on this pass: the 产品特点 section claims '相较于市场上现有主流产品，智铠100将提供2-3倍的实际使用性能' - 2-3x the actual real-world performance of existing mainstream products - and '平均迁移时间相较市场主流产品下降50%以上', plus '支持FP32、FP16、INT8等多精度推理混合计算' naming supported precisions with no number attached to any. flops stays EMPTY. A '2-3x' claim against an unnamed mainstream product is not a figure and must not become one. SPARSITY: no footnote, no '2:4', no sparsity wording. Moot, and recorded so a future reader does not assume a figure exists to be halved. OTHER VENDOR FACTS: multimedia - '最大128路视频解码（H.264@1080P 30 fps）', '支持H.264/H.265/VP9/AVS2', 'JPEG图像解码/编码：2000/500 帧（HD）'; '兼容CUDA生态'; 800+ general instructions; 200+ supported models on the training sibling. PROCESS NODE IS NULL because this page does not print one - the 7 nm figure belongs to the BI-V100, and carrying it over to this part would be exactly the kind of quiet inheritance this split exists to stop. MEMORY_BUS_WIDTH: STILL NULL, no vendor width or pin rate published, and NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.

Notes

CREATED BY THE SPLIT of iluvatar-bi-v100-mr-v100 on 2026-10-05, which held BI-V100 and MR-V100 in one record with a single memory_type. The two differ in memory technology (HBM2 vs HBM2E), power (250 W vs 150 W), slot width (dual vs single), role (training vs inference) and release year (2021 vs 2022), and the schema holds one memory_type per record, so a single record could not state either part correctly. WHY THE SPLIT IS WORTH MAKING RATHER THAN ANNOTATING: this card is the reason Iluvatar is in this repo at all. It ships HBM on an INFERENCE-ONLY card. The 产品规格 table, verbatim: '内存 | 16 GB HBM2E' (智铠50加速卡 MR-V50, '半长半高单槽 PCle 卡', '板级功耗 75W') and '32 GB HBM2E' (智铠100加速卡 MR-V100, '全长全高单槽 PCle', '板级功耗 150W'), interface 'PCle Gen4.0 X 16 lane'. Every other Chinese inference part in this repo is LPDDR - MLU370 at 307 GB/s, Ascend 310P at 204.8 GB/s - and even Moore Threads' S4000 is GDDR6, not HBM. HBM2E at inference power and inference pricing is a genuinely different proposition. NO COMPUTE FIGURE, verified on this pass: the 产品特点 section claims '相较于市场上现有主流产品，智铠100将提供2-3倍的实际使用性能' - 2-3x the actual real-world performance of existing mainstream products - and '平均迁移时间相较市场主流产品下降50%以上', plus '支持FP32、FP16、INT8等多精度推理混合计算' naming supported precisions with no number attached to any. flops stays EMPTY. A '2-3x' claim against an unnamed mainstream product is not a figure and must not become one. SPARSITY: no footnote, no '2:4', no sparsity wording. Moot, and recorded so a future reader does not assume a figure exists to be halved. OTHER VENDOR FACTS: multimedia - '最大128路视频解码（H.264@1080P 30 fps）', '支持H.264/H.265/VP9/AVS2', 'JPEG图像解码/编码：2000/500 帧（HD）'; '兼容CUDA生态'; 800+ general instructions; 200+ supported models on the training sibling. PROCESS NODE IS NULL because this page does not print one - the 7 nm figure belongs to the BI-V100, and carrying it over to this part would be exactly the kind of quiet inheritance this split exists to stop. MEMORY_BUS_WIDTH: STILL NULL, no vendor width or pin rate published, and NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.

Cross-references

Interconnect (1)