Mythic M1108 host interface is PCI Express 2.0 (Hackster.io report of Mythic AMP specs)

RETRIEVED 2026-10-04. Recorded as its own source because it is the only reachable document in the whole repo that states a PCIe generation for the Mythic M1108, and the accelerator record had been carrying an UNRESOLVABLE 'pcie' interconnect value as a direct result of not having read it. VERBATIM, on the chip's host interface: 'An additional four control tiles per chip provides an interface to the host system, over PCI Express 2.0.' VERBATIM, on the sampling form: 'Mythic is currently sampling the part in an evaluation kit form, with plans to release both full-size PCI Express and more compact PCIe M.2 form factor accelerators.' WHY THIS IS status:draft AND confidence 0.5: it is a third-party blog report, not a Mythic datasheet, and Mythic's own product page (mythic.ai, source mythic-m1108-product-page) publishes no PCIe generation at all. Per AGENTS.md a blog that cites no primary source is still a source but must be marked kind: blog and expected to carry lower confidence, which is what this record does. The repointing is nonetheless an improvement over an unresolvable reference, because 'PCI Express 2.0' is a stated fact from a named source rather than an untyped 'pcie' string that resolves to nothing - and because the evidence is internally consistent: a PCIe Gen 2 host interface is exactly what a 4 W analog compute-in-memory part designed for edge and automotive would carry, and it is far too slow for any scale-up fabric, which is consistent with this record's other fields. LANE COUNT IS NOT PUBLISHED, so none is recorded; the interconnect schema carries no lane-count field for an accelerator reference anyway. IF A FUTURE PASS FINDS A MYTHIC FIRST-PARTY DOCUMENT, this source should be superseded rather than kept alongside it, and the pcie-gen3 value on the accelerator record should be revisited - the two are NOT in conflict (PCIe 2.0 is the older generation), they are simply different generations, and no back-compatibility clause is published for this part. 2026-10-11: Re-read Hackster.io article. Confirms verbatim statement: 'An additional four control tiles per chip provides an interface to the host system, over PCI Express 2.0.' Retained at confidence 0.5 (draft) pending official Mythic datasheet.