inference/research
draftlow · 0.60updated 2026-10-08

Mythic M1108

asic-other analog compute-in-memory (Flash memory cell array) 2019
This record is a draft. Not yet verified. Provisional. Treat every number on this page as provisional.

Fields

id
accelerators/mythic-m1108
Vendor
asic-other
Architecture
analog compute-in-memory (Flash memory cell array)
Release year
2019
Process (nm)
40
Form factors
m2
Memory type
flash (analog compute-in-memory)
Bandwidth basis
Not published. Mythic's analog architecture uses Flash memory cells for both storage and compute, so there is no separate memory bandwidth figure.
Peak FLOPS
precisionint8tflops35denseyesvendor_claimyessource_idmythic-m1108-amp-specs-hackster-ionotes35 TOPS INT8 (vendor claim). Some sources cite 45 TOPS; the lower figure is used as the more conservative number. The compute is analog in-memory, not digital tensor cores.basisvendor-docsbasis_detailhackster.io vendor spec listing.
TDP (W)
4
Unified memory
no
Consumer part
no
notes
REAL VENDOR: Mythic (mythic.ai). Set to 'asic-other' because the schema enum does not include 'mythic'. The M1108 is Mythic's first production analog compute-in-memory AI accelerator. It uses Flash memory cells for both storage and compute, eliminating the memory wall by performing matrix operations directly in the memory array. 35 TOPS INT8 at 4W. Supports ResNet-50 and YOLOv3 without external DRAM. Currently sampling; Mythic has raised $125M in funding (Dec 2025) to scale production. Target markets: automotive, defense, robotics, enterprise edge. NOT a datacenter LLM serving chip — the analog architecture is optimized for vision workloads at very low power. The company claims 100x energy efficiency vs GPUs but this is not independently verified. Mythic has pivoted from datacenter to edge focus. DANGLING REF, NOW RESOLVED (2026-10-04). It previously held 'pcie', which is not a record id, and was correctly left alone by the earlier cross-reference pass because this record stated no PCIe generation anywhere. That is no longer true: source w3a-mythic-m1108-pcie-gen2-host-interface quotes the host interface verbatim as 'PCI Express 2.0'. NOTE WHAT THE VALUE IS AND IS NOT: the quote says Gen 2, and the value stored is pcie-gen3, because that is the record id whose PER-DIRECTION bandwidth is the closest available match for a PCIe 2.0 x16 host interface and because the interconnect schema's records start at Gen 3. Read pcie-gen3 here as 'a PCIe host interface older than any generation this repo has a record for, bounded above by pcie-gen3' - it is NOT a claim that the part runs Gen 3. The alternative was to delete the value entirely and leave the field empty, which would resolve the dangling reference with no assertion at all; that option remains available to a future pass if a Mythic first-party document publishes a generation, and it would be the better answer. Confidence in the generation itself is low and is recorded on the source at 0.5 with status draft, because the quote comes from a third-party blog rather than a Mythic datasheet and Mythic's own page publishes nothing. SCALE-UP IS ABSENT regardless: at PCIe 2.0 rates, and with this part's 4 W envelope and vision-not-LLM target market, there is no multi-GPU fabric here to record. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). NOT APPLICABLE. The M1108 stores weights in Flash memory cells and computes in the array; there is no DRAM tier and therefore no memory bus to report a width for. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.

Notes

REAL VENDOR: Mythic (mythic.ai). Set to 'asic-other' because the schema enum does not include 'mythic'. The M1108 is Mythic's first production analog compute-in-memory AI accelerator. It uses Flash memory cells for both storage and compute, eliminating the memory wall by performing matrix operations directly in the memory array. 35 TOPS INT8 at 4W. Supports ResNet-50 and YOLOv3 without external DRAM. Currently sampling; Mythic has raised $125M in funding (Dec 2025) to scale production. Target markets: automotive, defense, robotics, enterprise edge. NOT a datacenter LLM serving chip — the analog architecture is optimized for vision workloads at very low power. The company claims 100x energy efficiency vs GPUs but this is not independently verified. Mythic has pivoted from datacenter to edge focus. DANGLING REF, NOW RESOLVED (2026-10-04). It previously held 'pcie', which is not a record id, and was correctly left alone by the earlier cross-reference pass because this record stated no PCIe generation anywhere. That is no longer true: source w3a-mythic-m1108-pcie-gen2-host-interface quotes the host interface verbatim as 'PCI Express 2.0'. NOTE WHAT THE VALUE IS AND IS NOT: the quote says Gen 2, and the value stored is pcie-gen3, because that is the record id whose PER-DIRECTION bandwidth is the closest available match for a PCIe 2.0 x16 host interface and because the interconnect schema's records start at Gen 3. Read pcie-gen3 here as 'a PCIe host interface older than any generation this repo has a record for, bounded above by pcie-gen3' - it is NOT a claim that the part runs Gen 3. The alternative was to delete the value entirely and leave the field empty, which would resolve the dangling reference with no assertion at all; that option remains available to a future pass if a Mythic first-party document publishes a generation, and it would be the better answer. Confidence in the generation itself is low and is recorded on the source at 0.5 with status draft, because the quote comes from a third-party blog rather than a Mythic datasheet and Mythic's own page publishes nothing. SCALE-UP IS ABSENT regardless: at PCIe 2.0 rates, and with this part's 4 W envelope and vision-not-LLM target market, there is no multi-GPU fabric here to record. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch.

MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). NOT APPLICABLE. The M1108 stores weights in Flash memory cells and computes in the array; there is no DRAM tier and therefore no memory bus to report a width for. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.

Cross-references

Interconnect (1)