AMD Instinct MI300X / MI325X product pages - Infinity Fabric board rows and the 8-vs-7 link count (VERBATIM)

Board specification rows captured verbatim from BOTH CDNA 3 pages, which are identical on these rows. MI300X (https://www.amd.com/en/products/accelerators/instinct/mi300/mi300x.html): 'Bus Type: PCIe(R) 5.0 x16', 'Infinity Fabric(TM) Links: 8', 'Peak Infinity Fabric(TM) Link Bandwidth: 128 GB/s', 'Last Level Cache (LLC): 256 MB', 'Peak Memory Bandwidth: 5.3 TB/s'. MI325X (https://www.amd.com/en/products/accelerators/instinct/mi300/mi325x.html): 'Bus Type: PCIe(R) 5.0 x16', 'Infinity Fabric(TM) Links: 8', 'Peak Infinity Fabric(TM) Link Bandwidth: 128 GB/s', 'Peak Memory Bandwidth: 6 TB/s'. TWO POINTS THAT THIS ROW SET PROVES. (1) The label is 'Peak Infinity Fabric Link Bandwidth' with NO direction and NO indication of whether it is per link or a total - it is PER LINK and BIDIRECTIONAL, established from w7a-amd-cdna4-whitepaper-cdna3-lane-rate-32gbps (32 GT/s) and confirmed by 896 / 7 = 128 from the CDNA 4 white paper's CDNA 3 aggregate. (2) These CDNA 3 pages publish NO scale-up / scale-out row split, unlike the MI350X/MI355X pages - so on MI300X and MI325X the host-to-GPU figure cannot be read off the same table and must come from the ROCm architecture page instead. Companion to vb-amd-mi300x-product-page-spec-table, which covers the compute and memory rows of the same table.