AMD Infinity Fabric (CDNA 3 / MI300X-MI325X: 7-link mesh at 32 Gbps, 128 GB/s bidirectional per link; host PCIe Gen5 x16 at 128 GB/s)

PER LINK, PER DIRECTION, 16-WIDE, 32 Gbps. The lane rate for this generation is NOT published in any AMD CDNA 3 document - neither the MI300X/MI325X product pages nor the ROCm MI300 microarchitecture page states a signal rate; they give only a link count plus an unlabelled-direction peak. It is recovered from the CDNA 4 white paper's own generational comparison, which states verbatim: 'In the prior generation, these were split across four IODs and operated at 32Gbps.' AMD'S OWN DERIVATION FORMULA, CDNA 2 white paper endnote MI200-29: 'Peak theoretical inter GDC to GDC data transport rate performance is calculated by Baud Rate * # lanes * # directions * # links / 8 = GB/s per card.' The '# directions' multiplier is AMD confirming every figure in this endnote family is BIDIRECTIONAL. 32 x 16 / 8 = 64 GB/s per direction; 32 x 16 x 2 / 8 = 128 GB/s bidirectional, which is EXACTLY the MI300X board table's 'Peak Infinity Fabric(TM) Link Bandwidth: 128 GB/s'. THE 128 IS THEREFORE BIDIRECTIONAL, confirmed by an independent route: the CDNA 4 white paper's CDNA 3 aggregate is 'up to eight AMD Infinity Fabric links providing up to 896 GB/s peak aggregate peer-to-peer (P2P) and 1,024 total peak aggregate theoretical GPU transport rate bandwidth performance per GPU OAM module', and 896 / 7 = 128 exactly, i.e. the aggregate counts the SEVEN mesh edges. GPU-TO-GPU TOTAL: 896 GB/s P2P per OAM. *** THE 1,024 IS A DIFFERENT QUANTITY AGAIN: *** 1,024 - 896 = 128, and that 128 is the PCIe Gen5 x16 host link, so AMD's 'total peak aggregate theoretical GPU transport rate' = GPU-to-GPU P2P + host I/O, exactly reproducing the stated 1,024. HOST PATH: the ROCm MI300 page gives 'The MI300X OAMs attach to the host system via PCIe Gen 5 x16 links (yellow lines)' - one x16 per OAM. NOTE THE COLLISION: the per-link bidirectional fabric figure and the bidirectional host figure are BOTH 128 GB/s on this generation. They are equal by coincidence of PCIe Gen5 x16 and 32 Gbps x 16 lanes, not because they are the same path, and the CDNA 4 generation separates them onto different rows for exactly this reason.

GPU-to-GPU: a FULLY CONNECTED 8-GPU mesh, not a ring. The ROCm MI300 page states 'The GPUs are using seven high-bandwidth, low-latency AMD Infinity Fabric(TM) links (red lines) to form a fully connected 8-GPU system' - seven is the minimum for 8 nodes to be mutually connected, so this is a non-blocking all-to-all domain and the CDNA 2 ring topology is gone. Host path: PCIe Gen5 x16 per OAM, with the node figure showing '8 fully interconnected MI300X OAM modules connected to (optional) PCIe switches via retimers and HGX connectors'. *** WHY AMD'S OWN SOURCES DISAGREE ON THE LINK COUNT, AND WHICH IS RIGHT: *** the product board tables say 'Infinity Fabric(TM) Links: 8' while the architecture page says seven. Both are first-party and both are correct about different things: 896 / 128 = 7 reproduces the P2P aggregate with seven links, and the eighth is the separately-configured I/O link. The CDNA 4 white paper corroborates the split directly - 'Each GPU offers over 1TB/s of communication bandwidth within a node with one Infinity Fabric link configured for PCIe(R) Gen 5 to connect to I/O devices such as storage and networking' - so 8 total links = 7 scale-up + 1 I/O. This record stores link_count 7 (the scale-up mesh) and names the discrepancy rather than silently picking one.

None for scale-up - the 8-GPU domain is direct point-to-point. Optional PCIe SWITCHES exist on the host side only (via retimers and HGX connectors), which is the mechanism by which a server exposes more PCIe lanes than the root complexes provide; they do not switch GPU-to-GPU traffic.

*** THE CONFLATION THIS GENERATION IS MOST EXPOSED TO: *** on CDNA 3 the per-link bidirectional GPU-to-GPU figure and the bidirectional host-to-GPU figure are the SAME NUMBER, 128 GB/s. Any table that lists one 'bandwidth' column for MI300X is ambiguous in a way no arithmetic can fix - the two figures are equal and distinct. The per-direction GPU-to-GPU figure is 64 GB/s per link, 448 GB/s aggregated across the 7-link mesh. *** AMD DOES NOT PUBLISH, for this generation: *** (a) a signal rate in any CDNA 3 document - the 32 Gbps here comes from the CDNA 4 white paper's backward-looking sentence, which is AMD's own number but from the next generation's document, so a reader wanting CDNA-3-only provenance will not find it in a CDNA 3 file; (b) a 'Nth Gen AMD Infinity Architecture' label - the MI300X page's Supported Technologies row lists 'AMD Infinity Architecture' with no number, and the '4th Gen' label appears only from MI350X/MI355X onward, which is why this record is keyed to the CDNA generation; (c) separate scale-up and scale-out board rows - those appear only from MI350X/MI355X, so on MI300X the host and fabric figures must be read from different documents and cannot be separated by AMD's own labelling; (d) a node-level bisection bandwidth for the CDNA 3 package - AMD publishes one only for CDNA 4 (see amd-infinity-fabric-cdna4). INFERENCE RELEVANCE: 448 GB/s per direction against 5.3 TB/s of HBM3 is roughly 12:1, and the full mesh means no bisection penalty, so 8-way TP is topology-feasible on this generation where it was ring-limited on CDNA 2 - the fabric ratio against memory, not the per-link rate, is what decides TP viability.