AMD 'Introducing AMD CDNA 4 Architecture' white paper - prior-generation Infinity Fabric lane rate of 32 Gbps

The CDNA 4 white paper is the ONLY AMD document located that states a signal rate for the PRIOR generation's fabric. Verbatim from the communication/scaling section: 'The AMD CDNA 4 architecture comprises 8 AMD Infinity Fabric(TM) links that are 16-bits wide and fully bi-directional for inter-package communication within a single server node. In the prior generation, these were split across four IODs and operated at 32Gbps. The Infinity Fabric links in the AMD CDNA 4 architecture run up to 20% faster generationally at 38.4Gbps for a total link bandwidth of 76.8GB/s in each direction and each of the repartitioned IODs contains four links.' This closes the gap that AMD's own CDNA 3 material never closes: neither the MI300X/MI325X product pages nor the ROCm MI300 microarchitecture page publishes a lane rate at all, only a count (8 or 7) plus an unlabelled-direction peak of 128 GB/s. Applying AMD's own MI200-29 formula, 32 GT/s * 16 lanes * 2 directions / 8 = 128 GB/s bidirectional per link, which reproduces the MI300X board table's 128 exactly and confirms 32 Gbps is the CDNA 3 rate and that the 128 is bidirectional. It also explains the board table's '8 links' versus the architecture page's '7 links': 896 GB/s aggregate P2P / 128 per link = 7, so the P2P aggregate counts only the 7 mesh edges while the board table's 8 counts the seventh mesh link plus the separately-configured I/O link.