inference/research
verifiedhigh · 0.90updated 2026-10-03

AMD Instinct MI325X

amd CDNA3 (gfx942) 2024

Fields

id
accelerators/amd-instinct-mi325x
Vendor
amd
Architecture
CDNA3 (gfx942)
Release year
2024
Process (nm)
5
Form factors
oam
VRAM (GB)
256
Memory type
hbm3e
Memory bus (bit)
8,192
Memory bandwidth (GB/s)
6,000
Bandwidth basis
'Up to 6 TB/s' per the AMD spec table. Same 8192-bit interface as MI300X but HBM3E at a higher data rate (spec table 'Memory Clock 6 GHz'). AMD footnote MI325-001A gives 6 TB/s as an AMD Performance Labs calculation from 2024-09-26 'based on current specifications and/or estimation', so read it as ~6.0 TB/s theoretical, not measured.
Peak FLOPS
precisionfp32tflops163.4denseyesvendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp32 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:true as printed.precisiontf32tflops653.7denseyesvendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:true as printed.precisiontf32tflops1,307.4densenovendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own tf32 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp16tflops1,307.4denseyesvendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:true as printed.precisionfp16tflops2,614.9densenovendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp16 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionbf16tflops1,307.4denseyesvendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:true as printed.precisionbf16tflops2,614.9densenovendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own bf16 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionfp8tflops2,614.9denseyesvendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:true as printed.precisionfp8tflops5,229.8densenovendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own fp8 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.precisionint8tflops2,614.9denseyesvendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:true as printed.precisionint8tflops5,229.8densenovendor_claimyessource_idamd-mi325x-product-pagebasisvendor-spec-sheetbasis_detailTranscribed from the vendor's own int8 for AMD Instinct MI325X (source of record: 'AMD Instinct MI325X product page', kind: spec-sheet). Recorded dense:false - the vendor prints this as a structured-sparsity figure; the dense companion row on this record is the halved value. See this record's notes for the sparsity-footnote rule.
TDP (W)
1,000
Unified memory
no
Consumer part
no
notes
AUDIT 2026-10-03 (AMD convention check, and a genuine footnote caveat): AMD's 'Peak X Performance' = DENSE / 'with Structured Sparsity' = SPARSE at 2x rule (source acc2-amd-ml300-convention) is confirmed on the MI325X page: FP8 '2.61 PFLOPs'/'5.22 PFLOPs', FP16 '1.3'/'2.61', TF32 '653.7 TFLOPs'/'1.3 PFLOPs', INT8 '2.6 POPs'/'5.22 POPs', BF16 '1.3'/'2.61'. Every dense flag is correct. Unlike the MI300X, AMD's own comparison chart on the MI325X page labels the H200 SXM column WITHOUT the word sparsity - 'TF32 494.7 | 653.7', 'FP16/BF16 (Tensor/Matrix) 989.4 | 1307.4', 'FP8 1978.9 | 2614.9' - so on this page the H200 figures are printed as if dense. NVIDIA's own H200 page footnotes those same numbers as 'With sparsity'. AMD's chart and NVIDIA's spec table disagree about the H200's density, and both are primary vendor statements; that disagreement is a property of the sources, not of this record, and the H200 record carries NVIDIA's own footnote as authoritative for an NVIDIA part. AMD's 6 TB/s figure, as already noted, is a Performance Labs calculation footnote rather than a measured number. MI300X with more and faster memory, nothing else. Identical compute silicon: 304 CUs, 1216 matrix cores, 19,456 SPs, 2100 MHz, 153B transistors, same 8192-bit interface. The only changes are 256 GB HBM3E instead of 192 GB HBM3, 6 TB/s instead of 5.3 TB/s, and 1000W instead of 750W TBP. Same eight-XCD caveat as MI300X: 256 GB is one package-level address space across 8 compute dies, not two devices. Because the compute flops are identical to MI300X, ANY benchmark gap between the two parts is a pure memory capacity/bandwidth effect. This is the capacity sweet spot of the CDNA3 generation: 256 GB per OAM at 1000W, versus MI300X's 192 GB at 750W. ROCm LLVM target gfx942, identical to MI300X. 54V UBB, passive OAM, 8 Infinity Fabric links at 128 GB/s.

Notes

AUDIT 2026-10-03 (AMD convention check, and a genuine footnote caveat): AMD's 'Peak X Performance' = DENSE / 'with Structured Sparsity' = SPARSE at 2x rule (source acc2-amd-ml300-convention) is confirmed on the MI325X page: FP8 '2.61 PFLOPs'/'5.22 PFLOPs', FP16 '1.3'/'2.61', TF32 '653.7 TFLOPs'/'1.3 PFLOPs', INT8 '2.6 POPs'/'5.22 POPs', BF16 '1.3'/'2.61'. Every dense flag is correct. Unlike the MI300X, AMD's own comparison chart on the MI325X page labels the H200 SXM column WITHOUT the word sparsity - 'TF32 494.7 | 653.7', 'FP16/BF16 (Tensor/Matrix) 989.4 | 1307.4', 'FP8 1978.9 | 2614.9' - so on this page the H200 figures are printed as if dense. NVIDIA's own H200 page footnotes those same numbers as 'With sparsity'. AMD's chart and NVIDIA's spec table disagree about the H200's density, and both are primary vendor statements; that disagreement is a property of the sources, not of this record, and the H200 record carries NVIDIA's own footnote as authoritative for an NVIDIA part. AMD's 6 TB/s figure, as already noted, is a Performance Labs calculation footnote rather than a measured number. MI300X with more and faster memory, nothing else. Identical compute silicon: 304 CUs, 1216 matrix cores, 19,456 SPs, 2100 MHz, 153B transistors, same 8192-bit interface. The only changes are 256 GB HBM3E instead of 192 GB HBM3, 6 TB/s instead of 5.3 TB/s, and 1000W instead of 750W TBP.

Same eight-XCD caveat as MI300X: 256 GB is one package-level address space across 8 compute dies, not two devices.

Because the compute flops are identical to MI300X, ANY benchmark gap between the two parts is a pure memory capacity/bandwidth effect. This is the capacity sweet spot of the CDNA3 generation: 256 GB per OAM at 1000W, versus MI300X's 192 GB at 750W.

ROCm LLVM target gfx942, identical to MI300X. 54V UBB, passive OAM, 8 Infinity Fabric links at 128 GB/s.

Cross-references

Interconnect (3)