Version
CDNA2 (gfx90a, MI200) - the only generation for which AMD states a per-link rate
Bandwidth (GB/s, per link, unidirectional)
50
Bandwidth basis
PER LINK, UNIDIRECTIONAL, PER GENERATION. AMD's ROCm MI250 microarchitecture page states the link-layer rate directly: each 16-wide AMD Infinity Fabric link between GPUs 'can run at up to 25 GT/sec, which correlates to a peak transfer bandwidth of 50 GB/sec for a 16-wide link (two bytes per transaction)', and repeats 'a theoretical peak transfer rate of 50 GB/sec per link (or 100 GB/sec bidirectional peak transfer bandwidth)'. The recorded value is the per-direction 50 GB/s, NOT the 100 GB/s bidirectional figure. GENERATION DELTA: the 25 GT/sec / 50 GB/s per-link rate is the CDNA2 (gfx90a, MI210/MI250X) figure, and it is the ONLY per-link rate AMD states anywhere in the documents retrieved for this record. For CDNA3 (gfx942, MI300/MI325X) AMD publishes only a link count plus an aggregate 'Peak Infinity Fabric Link Bandwidth' (128 GB/s on the MI300X board table) with no signal rate and no direction, so no CDNA3 per-link value is asserted here - see amd-infinity-fabric-link, which carries those board figures and is status contested precisely because of the direction ambiguity. Direction caveat: unlike the Infinity Fabric board tables, this figure is direction-safe because AMD itself states both halves of it.
Topology
Point-to-point, no switch part. TWO distinct roles, and this is the part that is routinely misread: (1) DIE-TO-DIE, inside one package - on MI250X the two GCDs of one OAM module are joined by FOUR xGMI/Infinity Fabric links, which AMD gives as 4 x 25 GT/sec = 200 GB/sec peak transfer between the two GCDs, or 400 GB/sec bidirectional for the same; (2) DIE-TO-DEVICE, between accelerators - on MI210 (PCIe cards) xGMI is exposed through direct-connect xGMI BRIDGE CARDS in adjacent PCIe slots, giving dual and quad GPU hives, whereas the MI250X/MI250 OAM modules carry 8 links natively. On a multi-OAM MI300X node AMD's own architecture reference states the accelerator-side count is SEVEN Infinity Fabric links, used 'to form a fully connected 8-GPU system' - but the MI300X product page board table says 'Infinity Fabric Links: 8'. That is a real disagreement between two first-party AMD sources, not a typo: seven links is the minimum needed to make 8 nodes fully connected (each node needs a link to each of the other 7), so the board-table 8 is most likely counting an extra link of a different role (host or scale-out) rather than a mesh edge. Both figures are retained here; the typed link_count field carries the die-to-die value of 4 for MI250X, which is where this record's per-link rate is sourced. On CDNA3/MI300 the die-to-die topology is also a full mesh over up to 8 vertically stacked XCDs plus 4 I/O dies, so an MI300X is internally a single 8-way domain, not two halves.
Switching
None. Every xGMI path is a direct point-to-point link; there is no AMD xGMI switch part. Scale-out beyond the platform is handled by external networking (see ethernet-uec and infiniband-xdr), never by xGMI. The practical consequence is the same one that separates nvswitch-4 from nvlink-3: a direct-attached full mesh is non-blocking within its domain size (8 is the practical limit) but there is no fabric to grow past it, so a wider deployment must add nodes rather than GPUs.
notes
COMPLETED 2026-10-03, previously all-null. The name AMD actually uses in its architecture documentation for these links, and the reason this record exists separately from amd-infinity-fabric-link is that the two families are NOT the same thing: xGMI is the die-to-die / accelerator-to-accelerator LINK, while Infinity Fabric is the broader family name that AMD also uses for the host-side and CPU-side fabric (and, confusingly, for the on-package links on some parts). Keeping them separate is what lets the per-link rate be stated per generation. PER-GENERATION SUMMARY, all first-party: gfx90a / CDNA2 (MI210, MI250, MI250X) - 25 GT/sec per signal, 16-wide, 50 GB/s per link per direction, 100 GB/s bidirectional per link; MI250X uses 4 links between its two GCDs for 200 GB/s peak transfer between dies (400 GB/s bidirectional), and the board exposes 8 Infinity Fabric links at a peak of 100 GB/s each. gfx942 / CDNA3 (MI300X, MI325X) - the board table moves to 7 links with a peak of 128 GB/s, and AMD's MI300 microarchitecture page states seven links form a fully connected 8-GPU system. The CDNA3 board figures are recorded on amd-infinity-fabric-link, not here, because AMD publishes them as a link count plus an aggregate peak with no direction stated and no per-link rate; do not read the MI300X '128 GB/s' as a per-direction per-link number without resolving that ambiguity, which is why that record is status contested. INFERENCE RELEVANCE, and the reason this matters more than it looks: the die-to-die mesh is what makes a multi-die accelerator behave like ONE device rather than like a cluster. On MI250X, two 64 GB HBM2e stacks and two 220-CU dies are reachable over 200 GB/s of die-to-die bandwidth, so a model can be sharded across the dies with a fabric that is a small fraction of the 3.2 TB/s of local HBM bandwidth - the arithmetic-intensity penalty of crossing the fabric is real but bounded. On MI300X the same reasoning applies one level up, with eight XCDs inside one package. The consequence for sharding decisions is that an intra-package split is cheap and an inter-package split is comparatively expensive, so the natural first move for a model that does not fit on one die is still within the package. HISTORY NOTE: on the PCIe-card parts (MI100, MI210) AMD also shipped xGMI BRIDGE CARDS that let adjacent-slot cards form dual or quad hives - a materially different and much weaker scale-up story than the OAM mesh, and one that is easy to assume wrongly when reading a MI210-era hive diagram. Also note xGMI is distinct from AMD's CPU-side Infinity Fabric link between EPYC sockets, which is a different link with a different rate; do not merge the two.