AMD Radeon Instinct MI50X

AMD's MI50 datasheet spec table: 'Memory Interface 4,096-Bits, Memory Clock 1 GHz, Memory Bandwidth up to 1 TB/s'. 4096 bits x 2.0 Gbps effective / 8 = 1024 GB/s. Note the datasheet lists 'Memory Clock 1 GHz' - a base clock that doubles to the 2 Gbps effective per-pin rate; the 'up to' qualifier is AMD's.

CORRECTED 2026-10-03: the int8 row (53.6 TOPS, dense:true) has been REMOVED as unsourced. AMD's MI50 datasheet - the primary source cited by the surviving rows, fetched from the Wayback copy of amd.com/system/files/documents/radeon-instinct-mi50-datasheet.pdf and read directly on 2026-10-03 - prints in prose: 'Delivering up to 26.5 TFLOPS of native half-precision (FP16) or up to 13.3 TFLOPS single-precision (FP32) peak floating point performance and INT8 support'. It states that INT8 is SUPPORTED but publishes no INT8 throughput figure at all. The 53.6 figure (exactly 2x the 26.5 FP16 number) was almost certainly inferred by doubling FP16, which is exactly the kind of manufactured number this repo forbids: AMD never endorses it, and on MI100 - the next CDNA part - AMD's page shows INT8 at HALF the FP16 figure, not double. So the arithmetic pattern on Vega20 cannot be assumed. Nothing is substituted: this record now carries only the three figures AMD actually printed, with the INT8 gap stated rather than filled. AUDIT 2026-10-03 (dense/sparse convention check, other rows): AMD's convention - 'Peak X Performance' = dense, 'Peak X Performance with Structured Sparsity' = sparse at exactly 2x - is established across six Instinct pages (source acc2-amd-ml300-convention). The MI50 datasheet predates AMD's structured-sparsity labelling and prints no sparsity footnote anywhere, so the surviving FP32 13.3 and FP16 26.5 rows are correctly dense:true. Note the direction of the INT8 story flips within one generation: on this Vega20 part the widely-quoted 53.6 TOPS INT8 is 2x FP16, while on the CDNA1 MI100 that followed, AMD's page prints INT8 at 92.3 against FP16 at 184.6 - i.e. HALF. A reader who carries 'INT8 is 2x FP16 on AMD' forward from this record gets it backwards on every CDNA part. MI50X is the 32 GB SKU of the Vega20-based MI50; the MI50 name covers both 16 GB and 32 GB HBM2 cards. AMD's datasheet table gives the MI50 (16GB or 32GB) specs: 60 CUs / 3,840 SPs, up to 26.5 TFLOPS FP16, 13.3 TFLOPS FP32, 6.6 TFLOPS FP64, up to 53.6 TOPS INT8. Note the naming risk: AMD's own docs sometimes write 'MI50X' when the SKU table just says 'MI50' with a 16GB-or-32GB memory option. vram_gb here is set to 32 (the X suffix denotes the 32GB part) but the underlying silicon is identical, so the compute figures are the same for both SKUs. Genuinely notable for its era: 53.6 TOPS INT8 is 2x the FP16 figure, so this GCN5 part DOES have a real 8-bit advantage - the opposite of the CDNA2 parts later in this repo, where INT8 equals FP16. GCN5's matrix/vector INT8 units were the reason MI50 was a reasonable inference card in 2018-2020. Scale-up: TWO Infinity Fabric Links per card, which AMD derives as '23 GT/s x 2 (bytes) x 2 (directions) = 92 GB/s' per link, so 184 GB/s peak peer-to-peer per card, aggregated with PCIe 4.0 to 248 GB/s of card I/O. Direct-Connect GPU hives of four cards were the deployment model. This is an order of magnitude less scale-up bandwidth than the 7x128 GB/s mesh on MI300X. NOT ROCm-SUPPORTED TODAY. AMD's current ROCm system-requirements table lists 'AMD Instinct MI50 | N/A | GCN5.1 | gfx906 | Unsupported', with the same warning that prebuilt ROCm libraries are not officially supported and will cause runtime errors. The live AMD product page 404s; figures come from a Wayback capture of the MI50 datasheet dated 2021-01-12. For inference today: 32 GB of HBM2 at 1 TB/s, GCN5 matrix cores with no BF16, no FP8, no TF32, no structured sparsity. A 32GB card that cannot officially run ROCm. Superseded on every axis by MI100 (which adds real Matrix Cores and BF16) and then by MI300X.