Biren BR100 GPGPU (2-die OAM training accelerator)

PER CHIP, AS PUBLISHED. Biren's Hot Chips 34 presentation states '64GB HBM2E' and the flopper.io spec sheet (citing the same presentation) gives 1.6 TB/s. No direction convention is stated by the vendor. The figure is recorded exactly as published.

THE HIERARCHY POINT: the BR100 is a 2-die 7nm chiplet design on CoWoS packaging with 77 billion transistors, and its compute figures are 2022 launch-release numbers for a part that could not legally be manufactured at TSMC after October 2022 due to US export controls. Treat as historical claims, not shipping specs. HOT CHIPS 34 SPECIFICATIONS (primary vendor source, Mike Hong / Lingjie Xu, August 2022): 'Area 1074mm^2', '2 @7nm', 'TransistorCount 77Billion', 'HostInterface PCIe Gen5 x16 w/CXL', 'PeakPerformance 2048TOPS@INT8, 1024TFLOPS@BF16, 512TFLOPS@TF32+, 256TFLOPS@FP32', 'Memory 64GB HBM2E', 'Interconnections 8 BLink', '2.3TB/s external I/O bandwidth', 'FormFactor OAM with 550W MaxTDP'. CHIPLET DESIGN: 896 GB/s die-to-die interconnect, with the vendor claiming '30% more performance, 20% better yield compared with a monolithic design'. Over 300 MB on-chip SRAM. The presentation carries its own confidentiality legend ('Confidential. This document contains confidential information of BirenTechnology'), so it is a vendor primary source but a weak one to cite for a shipping configuration. Biren was added to the BIS Entity List in October 2023. The BR100 was reportedly modified to process less data so it would fall below the US export threshold. Vendor is 'asic-other' because 'biren' is not in the schema enum. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). The vendor publishes NO memory-bus width for this part, and none was back-computed from the published bandwidth. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH.[REPAIRED 2026-10-08 by w8-reverify. This sentence previously read '(2026-10-04). %s NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH' — a literal printf placeholder left in the JSON by the wave-3 pass (commit 9968769) across 34 accelerator records, and invisible to every check in this repo because validate.py never reads notes. The substitution text is the same boilerplate the 7 uncorrupted records in this family already carry, and it is only valid here because memory_bus_bit is null on every one of the 34, so "the vendor does not publish it" is the true state. A record with a non-null memory_bus_bit must NOT receive this filler.] That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either inference is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the note above names the specific document that was read and found not to carry it, so a future pass does not have to re-establish that from scratch. MEMORY_BUS_WIDTH: STILL NULL, AND HERE IS PRECISELY WHAT WAS LOOKED FOR (2026-10-04). Biren publishes no memory bus width for the BR100, BR104 or BILI 166 parts. The Hot Chips BR100 presentation is a floorplan-level talk and states capacity and the two-die topology, not an interface width. NO FIGURE WAS BACK-COMPUTED FROM BANDWIDTH. That is the standing rule for this field in this repo and it was applied to every null here rather than to a subset: a width derived by dividing a published aggregate bandwidth by an assumed or half-assumed per-pin rate is two inferences stacked on one number, and if either is wrong the record looks populated while being wrong. The correct state of this field is 'the vendor does not publish it', and the text above names the specific document read and found not to carry it, so a future pass does not have to re-establish that from scratch.